2.2.4.1.4 Global Clock Dynamic Contribution—P_CLOCK

SoC Mode

P_CLOCK = (P_AC1 + N_SPINE × P_AC2 + N_ROW × P_AC3 + N_S-CELL × P_AC4) × F_CLK

N_SPINE is the number of global spines used in the user design—guidelines are provided in the “Device Architecture” chapter of the SmartFusion FPGA Fabric User's Guide.

N_ROW is the number of VersaTile rows used in the design—guidelines are provided in the “Device Architecture” chapter of the SmartFusion FPGA Fabric User's Guide.

F_CLK is the global clock signal frequency.

N_S-CELL is the number of VersaTiles used as sequential modules in the design.

Standby Mode and Time Keeping Mode

P_CLOCK = 0W