15.4.15 PWM Generator x Event 1 Register
- Caution should be exercised when modifying these bits while PGxCON.ON
=
1; unexpected results may occur. - This source can optionally be used as a PCI input, PCI qualifier, PCI terminator or PCI terminator qualifier.
- These events are derived from the internal PWM generator time base comparison events.
- Care must be taken if the selected trigger is also selected by PGxIOCON1.CAPTRSEL[1:0].
| Name: | PGxEVT1 |
| Offset: | 0x1060, 0x10D4, 0x1148, 0x11BC |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FLT2IEN | FLT1IEN | CLIEN | FFIEN | SIEN | IEVTSEL[1:0] | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PWMPCI[2:0] | UPDTRG[1:0] | PGTRGSEL[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DACTREN2 | DACTREN1 | ADTR1OFS[4:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ADTR1PS[4:0] | ADTR1EN3 | ADTR1EN2 | ADTR1EN1 | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – FLT2IEN PCI Fault 2 Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Fault interrupt is enabled. |
0 |
Fault interrupt is disabled. |
Bit 30 – FLT1IEN PCI Fault 1 Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Fault interrupt is enabled. |
0 |
Fault interrupt is disabled. |
Bit 29 – CLIEN PCI Current Limit Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Current limit interrupt is enabled. |
0 |
Current limit interrupt is disabled. |
Bit 28 – FFIEN PCI Feed-Forward Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Feed-forward interrupt is enabled. |
0 |
Feed-forward interrupt is disabled. |
Bit 27 – SIEN PCI Sync Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Sync interrupt is enabled. |
0 |
Sync interrupt is disabled. |
Bits 25:24 – IEVTSEL[1:0] Interrupt Event Selection bits(1)
| Value | Description |
|---|---|
11 |
Time base interrupts are disabled (sync, Fault, current limit and feed-forward events can be independently enabled). |
10 |
Interrupts CPU at ADC Trigger 1 event |
01 |
Interrupts CPU at TRIGA compare event |
00 |
Interrupts CPU at EOC |
Bits 23:21 – PWMPCI[2:0] PWM PCI Source Selection bits(2)
| Value | Description |
|---|---|
| 111-100 | Reserved |
| 011 | PWM Generator #4 output is used as PCI signal. |
| 010 | PWM Generator #3 output is used as PCI signal. |
| 001 | PWM Generator #2 output is used as PCI signal. |
| 000 | PWM Generator #1 output is used as PCI signal. |
Bits 20:19 – UPDTRG[1:0] Update Trigger Select bits(1)
| Value | Description |
|---|---|
11 |
If PGxCON.MPERSEL = 1, then a write to the MPER register automatically sets the UPDATE bit. If PGxCON.MPERSEL = 0 then a write of PGxTRIGA register automatically sets UPDATE bit |
10 |
If PGxCON.MPHSEL = 1, then a write to the MPHASE register automatically sets the UPDATE bit. If PGxCON.MPHSEL = 0, then a write to the PGxPHASE register automatically sets the UPDATE bit. |
01 |
If PGxCON.MDCSEL = 1, then a write to the MDC register automatically sets the UPDATE bit. If PGxCON.MDCSEL = 0, then a write to the PGxDC register automatically sets the UPDATE bit. |
00 |
User must set the PGxSTAT.UPDREQ bit manually. |
Bits 18:16 – PGTRGSEL[2:0] PWM Generator Trigger Output Selection bits(1,3,4)
| Value | Description |
|---|---|
111 |
Reserved |
110 |
PGxTRIGF compare event is a PG Trigger |
101 |
PGxTRIGE compare event is a PG Trigger |
100 |
PGxTRIGD compare event is a PG Trigger |
011 |
PGxTRIGC compare event is a PG Trigger |
010 |
PGxTRIGB compare event is a PG Trigger |
001 |
PGxTRIGA compare event is a PG Trigger |
000 |
EOC event is PG Trigger; this selection is required to function if the cycle is terminated by Sync PCI. |
Bit 15 – DACTREN2 DAC Trigger Source is PGxTRIGE Compare Event Enable bit
| Value | Description |
|---|---|
| 1 | PGxTRIGE register compare event enabled as a trigger source for DAC Trigger |
| 0 | PGxTRIGE register compare event disabled as a trigger source for DAC Trigger |
Bit 14 – DACTREN1 DAC Trigger Source is PGxTRIGD Compare Event Enable bit
| Value | Description |
|---|---|
| 1 | PGxTRIGD register compare event enabled as a trigger source for DAC Trigger |
| 0 | PGxTRIGD register compare event disabled as a trigger source for DAC Trigger |
Bits 12:8 – ADTR1OFS[4:0] ADC Trigger 1 Offset Selection bits(1)
| Value | Description |
|---|---|
11111 |
Offset by 31 trigger events |
. . . |
. . . |
00010 |
Offset by 2 trigger events |
00001 |
Offset by 1 trigger event |
00000 |
No offset |
Bits 7:3 – ADTR1PS[4:0] ADC Trigger 1 Postscaler Selection bits(1)
| Value | Description |
|---|---|
11111 |
1:32 |
. . . |
. .
. |
00010 |
1:3 |
00001 |
1:2 |
00000 |
1:1 |
Bit 2 – ADTR1EN3 ADC Trigger 1 Source is PGxTRIGC Compare Event Enable bit(1)
| Value | Description |
|---|---|
1 |
PGxTRIGC register compare event is enabled as a trigger source for ADC Trigger 1 |
0 |
PGxTRIGC register compare event is disabled as a trigger source for ADC Trigger 1 |
Bit 1 – ADTR1EN2 ADC Trigger 1 Source is PGxTRIGB Compare Event Enable bit(1)
| Value | Description |
|---|---|
1 |
PGxTRIGB register compare event is enabled as a trigger source for ADC Trigger 1 |
0 |
PGxTRIGB register compare event is disabled as a trigger source for ADC Trigger 1 |
Bit 0 – ADTR1EN1 ADC Trigger 1 Source is PGxTRIGA Compare Event Enable bit(1)
| Value | Description |
|---|---|
1 |
PGxTRIGA register compare event is enabled as a trigger source for ADC Trigger 1 |
0 |
PGxTRIGA register compare event is disabled as a trigger source for ADC Trigger 1 |