15.4.22 PWM Generator x CL PCI 2 Register

Note:
  1. Caution should be used when modifying this register bit(s) while PGxCON.ON = 1; unexpected results may occur.
  2. If more than one bit is set, the selected PCI sources are OR’ed together.
  3. If the PCI software control has a higher priority than PSS, and if SWPCIM[1:0] = 2’b00 and SWPCI = 1’b1, a PCI event is generated regardless of PSS[31:0] content.
Name: PGxCLPCI2
Offset: 0x107C, 0x10F0, 0x1164, 0x11D8

Bit 3130292827262524 
 PSS[31:24] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 PSS[23:16] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 PSS[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 PSS[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31:0 – PSS[31:0]  PCI Source Selection bits(1,2,3)

Refer to Table 15-3 for device-specific PSS bit information.