This register cannot be modified
while PGxSTAT.UPDATE = 1.
If HREN = 0, the
four least significant bits are read as ‘0000’.
In variable phase PWM, if PGxPHASE + PGxDC ≥ PGxPER, the falling edge of the PWM
signal will be terminated at the period boundary as intended.
Name:
PGxPHASE
Offset:
0x1094, 0x1108, 0x117C,
0x11F0
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
PHASE[19:16]
Access
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit
15
14
13
12
11
10
9
8
PHASE[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PHASE[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 19:0 – PHASE[19:0]
PWM Generator x Phase Register bits(1,2,3)
DS70005629B
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
