15.4.10 PWM Event Output Control Register y

Note:

'y’ denotes a common instance (A-F).
This is the PWM generator output signal prior to output mode logic and any output override logic.
Event output signal pulse will be two system clocks when this bit is set and EVTySTRD = 1.
The event signal is stretched using the peripheral bus clock because different PWM Generators may be operating from different clock sources.

Name:	PWMEVTy
Offset:	0x1038, 0x103C, 0x1040, 0x1044, 0x1048, 0x104C


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	EVTyOEN	EVTyPOL	EVTySTRD	EVTySYNC		EVTyPGS[2:0]
Access	R/W	R/W	R/W	R/W		R/W	R/W	R/W
Reset	0	0	0	0		0	0	0


Bit	7	6	5	4	3	2	1	0
				EVTySEL[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bit 15 – EVTyOEN PWM Event Output Enable bit

Value	Description
`1`	Event output signal is output on the PWMEy pin.
`0`	Event output signal is internal only.

Bit 14 – EVTyPOL PWM Event Output Polarity

Value	Description
`1`	Event output signal is active-low.
`0`	Event output signal is active-high.

Bit 13 – EVTySTRD PWM Event Output Stretch Disable bit⁽⁴⁾

Value	Description
`1`	Event output signal pulse width is not stretched.
`0`	Event output signal is stretched to eight PWM clock cycles minimum.

Bit 12 – EVTySYNC PWM Event Output Sync bit⁽³⁾

Event output signal pulse will be synchronized to peripheral_clk.

Value	Description
`1`	Event output signal is synchronized to the system clock.
`0`	Event output is not synchronized to the system clock.

Bits 10:8 – EVTyPGS[2:0] PWM Event Source Selection bits

Value	Description
111-100	Reserved
011	PG4
010	PG3
001	PG2
0000	PG1

Bits 4:0 – EVTySEL[4:0] PWM Event Selection bits⁽²⁾

Value	Description
`11111-11110`	Reserved when FEP = 0

`11101`	MPLL Lock event signal (‘Reserved’ when HREN = 0)
`11100`	MPLL Lock Lost event signal (‘Reserved’ HREN = 0)
`11011`	MPLL Lock Time-Out event signal (‘Reserved’ when HREN = 0)
`11010`	Runt Pulse event signal (‘Reserved’ when HREN = 0)
`01100-11001`	Reserved
`01011`	DAC Trigger signal
`01010`	ADC Trigger 2 signal
`01001`	ADC Trigger 1 signal
`01000`	STEER signal (available in push-pull output modes only)
`00111`	PHASE signal (available in center aligned modes only)
`00110`	PCI Fault 2 active output signal
`00101`	PCI Fault 1 active output signal
`00100`	PCI Current Limit active output signal
`00011`	PCI Feed-Forward active output signal
`00010`	PCI Sync active output signal
`00001`	PWM generator output signal
`00000`	Source selected by PGTRGSEL [2:0] bits

DS70005629B

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