15.4.1 PWM Clock Control Register

Note:
  1. These bits cannot be modified while PCLKCON.LOCK = 1.
  2. These bits are not present when HREN = 0.
  3. User software may write a ‘0’ (after the bit has been set earlier) to this location to turn off and then turn on the PWM high-resolution FEP module. This will reinitialize the PWM high-resolution FEP module.
  4. These bits cannot be cleared by clearing the HREN bit. If it has been set prior to clearing the HREN bit, it has to be cleared manually prior to entering high-resolution operation.
  5. The PWM clock will also be connected to the clock generator 5 to support the high-resolution FEP. When high-resolution FEP is selected, the MCLKSEL control bits must be set to select the clock generator. Otherwise, unexpected results will occur.

Legend: C = Clearable bit

Name: PCLKCON
Offset: 0x1000

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 HRRDYHRERR     LOCK 
Access RR/C/HSR/W 
Reset 000 
Bit 76543210 
   DIVSEL[1:0] Reserved MCLKSEL 
Access R/WR/WR/WR/W 
Reset 0010 

Bit 15 – HRRDY  High-Resolution Ready bit(2)

ValueDescription
1 High-resolution circuitry is ready.
0 High-resolution circuitry is not ready.

Bit 14 – HRERR  High-Resolution Error bit(2,3,4)

ValueDescription
1 An error has occurred. PWM signals will have limited resolution.
0 No error has occurred. PWM signals will have full resolution when HRRDY = 1.

Bit 8 – LOCK Lock bit

ValueDescription
1

Write-protected registers and bits are locked.
0

Write-protected registers and bits are unlocked.

Bits 5:4 – DIVSEL[1:0]  PWM Clock Divider Selection bits(1)

ValueDescription
11

Divide ratio is 1:16
10

Divide ratio is 1:8
01

Divide ratio is 1:4
00

Divide ratio is 1:2

Bit 2 – Reserved  Maintain as ‘1’

Bit 0 – MCLKSEL  PWM Master Clock Selection bit(1,5)

Note: Do not change the MCLKSEL[1:0] bits while ON (PGxCON[15]) = 1.
ValueDescription
1 CKLGEN5
0 UPB clock