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15.4.29 PWM Generator x Duty Cycle Register
Note:
This register cannot be modified
while PGxSTAT.UPDATE = 1.
If HREN = 0, the
four least significant bits are read as ‘0000’.
In variable phase PWM, if PGxPHASE + PGxDC≥ PGxPER, the falling edge of the PWM
signal will be terminated at the period boundary as intended.
Name: PGxDC Offset: 0x1098, 0x110C, 0x1180,
0x11F4
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 DC[19:16] Access R/W R/W R/W R/W Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8 DC[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 DC[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bits 19:0 – DC[19:0]
PWM Generator x Duty Cycle Register bits(1,2,3,4)
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