3.4.4.8.2 Cache Miss, ISB Hit

In the event of a cache miss, the data will be sourced from the ISB buffer with a matching address tag.

Furthermore, the Cache will become busy for one cycle after the ISB hits while the data is transferred from the ISB buffer to the cache memory. The cache memory cannot be accessed by the CPU while data are written from the ISB to the cache. This could result in an unintentional cache miss on the following fetch cycle. However, the necessary program data will be available in the ISB so no stall cycles will occur due to this behavior. After the program data word is transferred to the cache memory, the ISB line will then be invalidated so that future fetches from that program word will occur from the cache memory and not the ISB.