3.4.4.8.3 Cache Miss and ISB Miss

If the program data is not available in the Instruction Cache or an ISB buffer, the PBU must then begin a new fetch from Flash program memory. The PBU waits for any existing fetches in progress to complete before starting the new fetch.

An LRU algorithm is used to determine which ISB slice is used for the fetch if more than one slice is implemented.

When the requested program word is available in the ISB, a cache write cycle is initiated to store the data in the appropriate Instruction Cache line as described in the prior Section and in Section 3.6.8.