Active Buffer Selection Policy

In order to maximize the efficiency of the ISB slices and to avoid discarding useful (or storing useless) data, several criteria are applied when selecting a new ISB slice for program flow.

To assist with this process, an internal prefetch valid flag is used to determine whether a prefetch is underway. It is asserted when the prefetch request from the PBU is granted by the NVM. It is negated when the prefetch completes, at which point the data will be stored in the ISB.

  1. When there is no address match on any of the buffer slices and no SSA match on any of the buffer slices, pick the LRU buffer as the active buffer.
  2. When there is an address match on more than one buffer slice and data is either valid on all or more than one of those buffer slices, pick the active buffer as the one with the lowest LRU value that has its data valid.
  3. When there is an address match on more than one buffer slice and data is valid on only one of those buffer slices, pick the active buffer as the one which has its data valid.
  4. When there is an address match on more than one buffer slice and data is not valid on any of those buffer slices but prefetch_valid is set on any one of them, pick the active buffer as the one that has its prefetch valid set (because it will be available for use faster).
  5. When there is an address match on more than one buffer slice and data is not valid on any of those buffer slices and prefetch_valid is not set on any of them, pick the active buffer as the one with the lowest LRU value that has an address match.
  6. When there is an address match on only one buffer slice, but data is not valid on that buffer slice and prefetch_valid is not set on that buffer slice, pick the one that had an address match as the active buffer.
  7. When there is no address match on any of the buffer slices but an SSA match on any one buffer slice, pick the buffer slice that had an SSA match as the active buffer. This will help reduce thrashing of the ISB buffer slices. This behavior will improve ISB performance when a certain section of code is looped repeatedly. The same ISB will get reused when the code flow branches to the beginning of the loop instead of overwriting the contents of another ISB buffer slice.
  8. When there is no address match on any of the buffer slices but an ISB slice error on any one or multiple buffer slices, pick a buffer slice that had an error as the active buffer. This buffer slice was preloaded with cache data that failed parity check and hence these data are unusable. Therefore, the slice may as well be reused for another instruction flow.