18.3 SENT Control/Status Registers
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| 0x80 | SENT1CON1L | 15:8 | SNTEN | SNTSIDL | RCVEN | TXM | TXPOL | CRCEN | ||
| 7:0 | PPP | SPCEN | PS | NIBCNT[2:0] | ||||||
0x82 ... 0x83 | Reserved | |||||||||
| 0x84 | SENT1CON2L | 15:8 | SENT1CON2[15:8] | |||||||
| 7:0 | SENT1CON2[7:0] | |||||||||
0x86 ... 0x87 | Reserved | |||||||||
| 0x88 | SENT1CON3L | 15:8 | SENT1CON3[15:8] | |||||||
| 7:0 | SENT1CON3[7:0] | |||||||||
0x8A ... 0x8B | Reserved | |||||||||
| 0x8C | SENT1STATL | 15:8 | ||||||||
| 7:0 | PAUSE | NIB[2:0] | CRCERR | FRMERR | RXIDLE | SYNCTXEN | ||||
0x8E ... 0x8F | Reserved | |||||||||
| 0x90 | SENT1SYNC | 15:8 | SENTSYNC[15:8] | |||||||
| 7:0 | SENTSYNC[7:0] | |||||||||
0x92 ... 0x93 | Reserved | |||||||||
| 0x94 | SENT1DATL | 15:8 | DATA4[3:0] | DATA5[3:0] | ||||||
| 7:0 | DATA6[3:0] | CRC[3:0] | ||||||||
| 0x96 | SENT1DATH | 15:8 | STAT[3:0] | DATA1[3:0] | ||||||
| 7:0 | DATA2[3:0] | DATA3[3:0] | ||||||||