20.6.4 CCPx Control 2 Low Register
| Name: | CCPxCON2L |
| Offset: | 0x954, 0x978, 0x99C, 0x9C0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PWMRSEN | ASDGM | SSDG | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ASDG[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 15 – PWMRSEN CCPx PWM Restart Enable bit
| Value | Description |
|---|---|
1 |
ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input has ended. |
0 |
ASEVT bit must be cleared in software to resume PWM activity on output pins. |
Bit 14 – ASDGM CCPx Auto-Shutdown Gate Mode Enable bit
| Value | Description |
|---|---|
1 |
Waits until the next Time Base Reset or rollover for shutdown to occur. |
0 |
Shutdown event occurs immediately. |
Bit 12 – SSDG CCPx Software Shutdown/Gate Control bit
| Value | Description |
|---|---|
1 |
Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting of ASDGM bit still applies). |
0 |
Normal module operation. |
Bits 7:0 – ASDG[7:0] CCPx Auto-Shutdown/Gating Source Enable bits
| Value | Description |
|---|---|
1 |
ASDGx Source n is enabled (see Auto-Shutdown and Gating Sources for auto-shutdown/gating sources). |
0 |
ASDGx Source n is disabled. |