20.6.1 CCPx Control 1 Low Register
| Name: | CCPxCON1L |
| Offset: | 0x950, 0x974, 0x998, 0x9BC |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CCPON | CCPSIDL | CCPSLP | TMRSYNC | CLKSEL[2:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TMRPS[1:0] | T32 | CCSEL | MOD[3:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 15 – CCPON CCPx Module Enable bit
| Value | Description |
|---|---|
1 |
Module is enabled with an operating mode specified by the MOD[3:0] control bits. |
0 |
Module is disabled. |
Bit 13 – CCPSIDL CCPx Stop in Idle Mode bit
| Value | Description |
|---|---|
1 |
Discontinues module operation when device enters Idle mode. |
0 |
Continues module operation in Idle mode. |
Bit 12 – CCPSLP CCPx Sleep Mode Enable bit
| Value | Description |
|---|---|
1 |
Module continues to operate in Sleep modes. |
0 |
Module does not operate in Sleep modes. |
Bit 11 – TMRSYNC Time Base Clock Synchronization bit
| Value | Description |
|---|---|
1 |
Asynchronous module time base clock is selected and synchronized to the internal
system clocks (CLKSEL[2:0] ≠ |
0 |
Synchronous module time base clock is selected and does not require
synchronization (CLKSEL[2:0] = |
Bits 10:8 – CLKSEL[2:0] CCPx Time Base Clock Select bits
| Value | Description |
|---|---|
111 |
PPS TCKIx input |
110 |
CLC4 out |
101 |
CLC3 out |
100 |
CLC2 out |
011 |
CLC1 out |
010 |
FOSC |
001 |
Reference Clock (REFCLKO) |
000 |
FP |
Bits 7:6 – TMRPS[1:0] Time Base Prescale Select bits
| Value | Description |
|---|---|
11 |
1:64 Prescaler |
10 |
1:16 Prescaler |
01 |
1:4 Prescaler |
00 |
1:1 Prescaler |
Bit 5 – T32 32-Bit Time Base Select bit
| Value | Description |
|---|---|
1 |
Uses 32-bit time base for timer, single edge output compare or input capture function. |
0 |
Uses 16-bit time base for timer, single edge output compare or input capture function. |
Bit 4 – CCSEL Capture/Compare Mode Select bit
| Value | Description |
|---|---|
1 |
Input capture peripheral. |
0 |
Output Compare/PWM/Timer peripheral (exact function is selected by the MOD[3:0] bits). |
Bits 3:0 – MOD[3:0] CCPx Mode Select bits
For CCSEL = 1 (Input Capture modes):
| Value | Description |
|---|---|
1xxx |
Reserved |
011x |
Reserved |
0101 |
Capture every 16th rising edge. |
0100 |
Capture every 4th rising edge. |
0011 |
Capture every rising and falling edge. |
0010 |
Capture every falling edge. |
0001 |
Capture every rising edge. |
0000 |
Capture every rising and falling edge (Edge Detect mode). |
For CCSEL = 0 (Output Compare/Timer modes):
| Value | Description |
|---|---|
1111 |
External Input mode: Pulse generator is disabled, source is selected by ICS[2:0]. |
1110 |
Reserved |
110x |
Reserved |
10xx |
Reserved |
0111 |
Reserved |
0110 |
Reserved |
0101 |
Dual Edge Compare mode, buffered |
0100 |
Dual Edge Compare mode |
0011 |
16-Bit/32-Bit Single Edge mode, toggles output on compare match. |
0010 |
16-Bit/32-Bit Single Edge mode, drives output low on compare match. |
0001 |
16-Bit/32-Bit Single Edge mode, drives output high on compare match. |
0000 |
16-Bit/32-Bit Timer mode, output functions are disabled. |