20.6.2 CCPx Control 1 High Register
- This control bit has no function in Input Capture modes.
- This control bit has no
function when TRIGEN =
0. - Output postscale settings,
from 1:5 to 1:16 (
0100-1111), will result in a FIFO buffer overflow in Input Capture modes.
| Name: | CCPxCON1H |
| Offset: | 0x952, 0x976, 0x99A, 0x9BE |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| OPSSRC | RTRGEN | OPS3[3:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRIGEN | ONESHOT | ALTSYNC | SYNC[4:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 15 – OPSSRC Output Postscaler Source Select bit(1)
| Value | Description |
|---|---|
1 |
Output postscaler scales module trigger output events. |
0 |
Output postscaler scales time base interrupt events. |
Bit 14 – RTRGEN Retrigger Enable bit(2)
| Value | Description |
|---|---|
1 |
Time base can be retriggered when TRIGEN bit = |
0 |
Time base may not be retriggered when TRIGEN bit = |
Bits 11:8 – OPS3[3:0] CCPx Interrupt Output Postscale Select bits(3)
| Value | Description |
|---|---|
1111 |
Interrupt every 16th time base period match. |
1110 |
Interrupt every 15th time base period match. |
| . . . | |
0100 |
Interrupt every 5th time base period match. |
0011 |
Interrupt every 4th time base period match or 4th input capture event. |
0010 |
Interrupt every 3rd time base period match or 3rd input capture event. |
0001 |
Interrupt every 2nd time base period match or 2nd input capture event. |
0000 |
Interrupt after each time base period match or input capture event. |
Bit 7 – TRIGEN CCPx Trigger Enable bit
| Value | Description |
|---|---|
1 |
Trigger operation of time base is enabled. |
0 |
Trigger operation of time base is disabled. |
Bit 6 – ONESHOT One-Shot Trigger Mode Enable bit
| Value | Description |
|---|---|
1 |
One-Shot Trigger mode is enabled; trigger duration is set by OSCNT[2:0]. |
0 |
One-Shot Trigger mode is disabled. |
Bit 5 – ALTSYNC CCPx Clock Select bits
| Value | Description |
|---|---|
1 |
An alternate signal is used as the module synchronization output signal. |
0 |
The module synchronization output signal is the Time Base Reset/rollover event. |