20.6.8 CCPx Status Register

Legend: C = Clearable bit; W1 = Write ‘1’ Only bit

Name:	CCPxSTATL
Offset:	0x95C, 0x980, 0x9A4, 0x9C8


Bit	15	14	13	12	11	10	9	8
						ICGARM
Access						W1
Reset						0


Bit	7	6	5	4	3	2	1	0
	CCPTRIG	TRSET	TRCLR	ASEVT	SCEVT	ICDIS	ICOV	ICBNE
Access	R	W1	W1	R/C	R/C	R/C	R/C	R/C
Reset	0	0	0	0	0	0	0	0

Bit 10 – ICGARM Input Capture Gate Arm bit

A write of ‘1’ to this location will arm the input capture gating logic for a one-shot gate event when ICGSM[1:0] = 01 or 10. Bit always reads as ‘0’.

Bit 7 – CCPTRIG CCPx Trigger Status bit

Value	Description
`1`	Timer has been triggered and is running.
`0`	Timer has not been triggered and is held in Reset.

Bit 6 – TRSET CCPx Trigger Set Request bit

Writes ‘1’ to this location to trigger the timer when TRIGEN = 1 (location always reads as ‘0’).

Bit 5 – TRCLR CCPx Trigger Clear Request bit

Writes ‘1’ to this location to cancel the timer trigger when TRIGEN = 1 (location always reads as ‘0’).

Bit 4 – ASEVT CCPx Auto-Shutdown Event Status/Control bit

Value	Description
`1`	A shutdown event is in progress; CCPx outputs are in the Shutdown state.
`0`	CCPx outputs operate normally.

Bit 3 – SCEVT Single Edge Compare Event Status bit

Value	Description
`1`	A single edge compare event has occurred.
`0`	A single edge compare event has not occurred.

Bit 2 – ICDIS Input Capture x Disable bit

Value	Description
`1`	Event on Input Capture x pin (ICx) does not generate a capture event.
`0`	Event on Input Capture x pin will generate a capture event.

Bit 1 – ICOV Input Capture x Buffer Overflow Status bit

Value	Description
`1`	The Input Capture x FIFO buffer has overflowed.
`0`	The Input Capture x FIFO buffer has not overflowed.

Bit 0 – ICBNE Input Capture x Buffer Status bit

Value	Description
`1`	Input Capture x buffer has data available.
`0`	Input Capture x buffer is empty.