17.5.2 I2C1 Control Register High

Name: I2C1CONH
Offset: 0x202

Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
  PCIESCIEBOENSDAHTSBCDEAHENDHEN 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 6 – PCIE  Stop Condition Interrupt Enable bit

ValueDescription
1

Enables interrupt on detection of Stop condition.
0

Stop detection interrupts are disabled.

Bit 5 – SCIE  Start Condition Interrupt Enable bit

ValueDescription
1

Enables interrupt on detection of Start or Restart conditions.
0

Start detection interrupts are disabled.

Bit 4 – BOEN  Buffer Overwrite Enable bit

ValueDescription
1

I2CxRCV is updated, and an ACK is generated for a received address/data byte, ignoring the state of the I2COV bit only if the RBF bit = 0.
0

I2CxRCV is only updated when I2COV is clear.

Bit 3 – SDAHT SDAx Hold Time Selection bit

ValueDescription
1

Minimum of 300 ns hold time on SDAx after the falling edge of SCLx.
0

Minimum of 100 ns hold time on SDAx after the falling edge of SCLx.

Bit 2 – SBCDE Client Mode Bus Collision Detect Enable bit

If, on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the BCL bit is set and the bus goes Idle. This Detection mode is only valid during data and ACK transmit sequences.
ValueDescription
1

Enables Client bus collision interrupts.
0

Client bus collision interrupts are disabled.

Bit 1 – AHEN  Address Hold Enable bit

ValueDescription
1

Following the eighth falling edge of SCLx for a matching received address byte; SCLREL bit (I2CxCONL[12]) will be cleared and SCLx will be held low.
0

Address holding is disabled.

Bit 0 – DHEN  Data Hold Enable bit

ValueDescription
1

Following the eighth falling edge of SCLx for a received data byte; Client hardware clears the SCLREL bit (I2CxCONL[12]) and SCLx is held low.
0

Data holding is disabled.