17.5.1 I2C1 Control Register Low

Note:

Automatically cleared to ‘0’ at the beginning of Client transmission; automatically cleared to ‘0’ at the end of Client reception.
Automatically cleared to ‘0’ at the beginning of Client transmission.

Legend: HC = Hardware Clearable bit

Name:	I2C1CONL
Offset:	0x200


Bit	15	14	13	12	11	10	9	8
	I2CEN		I2CSIDL	SCLREL	STRICT	A10M	DISSLW	SMEN
Access	R/W		R/W/HC	R/W	R/W	R/W	R/W	R/W
Reset	0		0	1	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	GCEN	STREN	ACKDT	ACKEN	RCEN	PEN	RSEN	SEN
Access	R/W	R/W	R/W	R/W/HC	R/W/HC	R/W/HC	R/W/HC	R/W/HC
Reset	0	0	0	0	0	0	0	0

Bit 15 – I2CEN I2C1 Enable bit (writable by software only)

Value	Description
`1`	Enables the I2C1 module and configures the SDAx and SCLx pins as serial port pins.
`0`	Disables the I2C1 module; all I²C pins are controlled by port functions.

Bit 13 – I2CSIDL I2C1 Stop in Idle Mode bit

Value	Description
`1`	Discontinues module operation when device enters Idle mode.
`0`	Continues module operation in Idle mode.

Bit 12 – SCLREL SCLx Release Control bit (I²C Client mode only)⁽¹⁾

If STREN = 1:⁽²⁾

User software may write ‘0’ to initiate a clock stretch and write ‘1’ to release the clock. Hardware clears at the beginning of every client data byte transmission. Hardware clears at the end of every client address byte reception. Hardware clears at the end of every client data byte reception.


Value	Description
`1`	Releases the SCLx clock.
`0`	Holds the SCLx clock low (clock stretch).

If STREN = 0:

User software may only write ‘1’ to release the clock. Hardware clears at the beginning of every Client data byte transmission. Hardware clears at the end of every Client address byte reception.


Value	Description
`1`	Releases the SCLx clock.
`0`	Holds the SCLx clock low (clock stretch).

Bit 11 – STRICT I2C1 Strict Reserved Address Rule Enable bit

Value Description

Value	Description
`1`	Strict Reserved Addressing is enforced; for reserved addresses. (In Client Mode) – The device doesn’t respond to reserved address space and addresses falling in that category are NACKed. (In Host Mode) – The device is allowed to generate addresses with reserved address space.
`0`	Reserved Addressing would be Acknowledged. (In Client Mode) – The device will respond to an address falling in the reserved address space. When there is a match with any of the reserved addresses, the device will generate an ACK. (In Host Mode) – Reserved.

1

Strict Reserved Addressing is enforced; for reserved addresses.

(In Client Mode) – The device doesn’t respond to reserved address space and addresses falling in that category are NACKed.

(In Host Mode) – The device is allowed to generate addresses with reserved address space.

0

Reserved Addressing would be Acknowledged.

(In Client Mode) – The device will respond to an address falling in the reserved address space. When there is a match with any of the reserved addresses, the device will generate an ACK.

(In Host Mode) – Reserved.

Bit 10 – A10M 10-Bit Client Address Flag bit

Value	Description
`1`	I2CxADD is a 10-bit Client address.
`0`	I2CxADD is a 7-bit Client address.

Bit 9 – DISSLW Slew Rate Control Disable bit

Value	Description
`1`	Slew rate control is disabled for Standard Speed mode (100 kHz, also disabled for 1 MHz mode).
`0`	Slew rate control is enabled for High-Speed mode (400 kHz).

Bit 8 – SMEN SMBus Input Levels Enable bit

Value	Description
`1`	Enables input logic so that thresholds are compliant with the SMBus specification.
`0`	Disables SMBus-specific inputs.

Bit 7 – GCEN General Call Enable bit (in I²C Client mode only)

Value	Description
`1`	Enables interrupt when a general call address is received in I2CxRSR; the module is enabled for reception.
`0`	General call address is disabled.

Bit 6 – STREN SCL1 Clock Stretch Enable bit

In I²C Client mode only; used in conjunction with the SCLREL bit.

Value	Description
`1`	Enables clock stretching.
`0`	Disables clock stretching.

Bit 5 – ACKDT Acknowledge Data bit

In I²C Host mode during Host Receive mode. The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.

In I²C Client mode when AHEN = 1 or DHEN = 1, the value that the Client will transmit when it initiates an Acknowledge sequence at the end of an address or data reception.

Value	Description
`1`	NACK is sent.
`0`	ACK is sent.

Bit 4 – ACKEN Acknowledge Sequence Enable bit

In I²C Host mode only; applicable during Host Receive mode.

Value	Description
`1`	Initiates the Acknowledge sequence on SDAx and SCLx pins and transmits the ACKDT data bit.
`0`	Acknowledge sequence is Idle.

Bit 3 – RCEN Receive Enable bit (in I²C Host mode only)

Value	Description
`1`	Enables Receive mode for I²C; automatically cleared by hardware at the end of the 8-bit received data byte.
`0`	Receive sequence is not in progress.

Bit 2 – PEN Stop Condition Enable bit (in I²C Host mode only)

Value	Description
`1`	Initiates Stop condition on SDAx and SCLx pins.
`0`	Stop condition is Idle.

Bit 1 – RSEN Restart Condition Enable bit (in I²C Host mode only)

Value	Description
`1`	Initiates Restart condition on SDAx and SCLx pins.
`0`	Restart condition is Idle.

Bit 0 – SEN Start Condition Enable bit (in I²C Host mode only)

Value	Description
`1`	Initiates Start condition on SDAx and SCLx pins.
`0`	Start condition is Idle.