14.6.3.8 Bit Time Configuration Example

The following tables illustrate the configuration of the CAN FD Bit Time registers, assuming there is a CAN FD network in an automobile with the following parameters:

  • 500 kbps NBR – Sample Point at 80%
  • 2 Mbps DBR – Sample Point at 80%
  • 40 Meters – Minimum Bus Length

Table 14-6 and Table 14-7 illustrate how the bit time parameters are calculated. Since the parameters depend on multiple constraints and equations, and are calculated using an iterative process, it is recommended to enter the equations in a spreadsheet.

Table 14-8 translates the calculated values into register values. It is recommended to let the CAN FD Protocol Module measure the Transmitter Delay Compensation Value (TDCV). This is accomplished by setting TDCMOD[1:0] (CxTDC[1:0]) = 10 (Automatic mode). In order to set the SSP to 80%, TDCO[6:0] are set to (DBRP * DTSEG1).

Table 14-6. Step-by-Step Nominal Bit Rate Configuration
ParameterConstraintValueUnitEquations and Comments
NBTNBT ≥ 1 µs2µsEquation 14-1
FCANFCAN ≤ 80 MHz80MHzCAN clock frequency= 80 MHz
NBRP1 to 2561—Select smallest possible BRP value to maximize resolution.
NTQNBT, FCAN12.5nsEquation 14-3
NBT/NTQ4 to 385160—Equation 14-5
NSYNCFixed1NTQDefined in ISO11898-1:2015.
NPRSEGNPRSEG > TPROP95NTQEquation 14-9: TPROP = 910 ns, 
minimum NPRSEG = TPROP/NTQ = 72.8 NTQ. 
Selecting 95 will allow up to a 60m bus length.
NTSEG12 to 256 NTQ127NTQEquation 14-7. Select NTSEG1 to achieve 80% NSP.
NTSEG21 to 128 NTQ32NTQThere are 32 NTQ left to reach NBT/NTQ = 160.
NSJW1 to 128 NTQ;

SJW ≤ min (NPHSEG1, NPHSEG2)

32NTQMaximizing NSJW lessens the requirement for the oscillator tolerance.
Table 14-7. Step-by-Step Data Bit Rate Configuration
ParameterConstraintValueUnitEquations and Comments
DBTDBT ≥ 125 ns500nsEquation 14-2
DBRP1 to 2561—Selecting the same prescaler as for NBT ensures that the TQ resolution does not change during the Bit Rate Switching.
DTQDBT, FCAN12.5nsEquation 14-4
DBT/DTQ3 to 4940—Equation 14-6
DSYNCFixed1DTQDefined in ISO11898-1:2015.
DTSEG11 to 32 DTQ31DTQEquation 14-7. Select DTSEG1 to achieve 80% DSP.
DTSEG21 to 16 DTQ8DTQThere are 8 DTQ left to reach DBT/DTQ = 40.
DSJW1 to 16 DTQ;

SJW ≤ min (DPHSEG1, DPHSEG2)

8DTQMaximizing DSJW lessens the requirement for the 
oscillator tolerance.
Oscillator Tolerance

Conditions 1-5

Minimum of Conditions 1-50.78%Equation 14-11 through Equation 14-16
Table 14-8. Bit Time Register Initialization (500k/2M)
CxNBTCFGL/HValueCxDBTCFGL/HValueCxTDCL/HValue
BRP[7:0]0BRP[7:0]0TDCMOD[1:0]2
TSEG1[7:0]126TSEG1[4:0]30TDCO[6:0]31
TSEG2[6:0]31TSEG2[3:0]7TDCV[5:0]0
SJW[6:0]31SJW[3:0]7——