14.6.3 CAN FD Bit Time Configuration

In order to achieve higher bandwidth, bits in a CAN FD frame are transmitted with two different bit rates:

• Nominal Bit Rate (NBR): Used during arbitration until the sample point of the BRS bit and the sample point of the CRC delimiter reach the End of Frame (EOF).
• Data Bit Rate (DBR): Used during the data and CRC field.

NBR is limited by the propagation delay of the CAN network (see Propagation Delay). In the data phase, only one transmitter remains; therefore, the bit rate can be increased. The transmitting node always compares the intended transmitted bits with the actual bits on the CAN bus. The propagation delay in the data phase can be longer than the bit time. In this case, the data bits are sampled at a Secondary Sample Point (SSP) (see Transmitter Delay Compensation (TDC)).

NBR is the number of bits per second during the arbitration phase. It is the inverse of the Nominal Bit Time (NBT) (see Equation 14-1).

DBR is the number of bits per second during the data phase. It is the inverse of the Data Bit Time (DBT) (see Equation 14-2).

The Baud Rate Prescaler (BRP) is used to divide the Fcan. The divided Fcan is used to generate the bit times.

There are two prescalers: NBRP for the Nominal Bit Rate Prescaler and DBRP for the Data Bit Rate Prescaler. The Time Quanta (NTQ and DTQ) are selected as shown in Equation 14-3 and Equation 14-4.

CAN bit times have four segments (see Figure 14-11).

Synchronization Segment (SYNC) – Synchronizes the different nodes connected on the CAN bus. A bit edge is expected to be within this segment. The Synchronization Segment is always 1 Tq.

Propagation Segment (PRSEG) – Compensates for the propagation delay on the bus. PRSEG has to be longer than the maximum propagation delay.

Phase Segment 1 (PHSEG1) – Compensates for errors that may occur due to phase shifts in the edges. The time segment may be automatically lengthened during resynchronization to compensate for the phase shift.

Phase Segment 2 (PHSEG2) – Compensates for errors that may occur due to phase shifts in the edges. The time segment may be automatically shortened during resynchronization to compensate for the phase shift.

In the Bit Time registers, PRSEG and PHSEG1 are combined to create TSEG1. PHSEG2 is called TSEG2. Each segment has multiple Time Quanta (Tq). The sample point lies between TSEG1 and TSEG2.

Table 14-4 and Table 14-5 show the ranges for the bit time configuration parameters.

The total number of Tq in a bit time is programmable and can be calculated using Equation 14-5 and Equation 14-6.