14.6.4.4 Receive FIFO Configuration

FIFO 1 through FIFO 31 can be configured as receive FIFOs by clearing TXEN in the CxFIFOCONx register. The number of message objects in each receive FIFO is configured using the FSIZE[4:0] bits (CxFIFOCONx[28:24]). All objects in one receive FIFO use the same payload size (number of data bytes), which is determined by the PLSIZE[2:0] bits (CxFIFOCONx[31:29]). Received messages can be time-stamped by setting the RXTSEN bit (CxFIFOCONx[5]).