3.2.17 CPU STATUS Register(1)
Note:
- The CPU STATUS register is not memory mapped. The IPL3 bit is concatenated with the IPL[2:0] bits (SR[7:5]) to form the CPU Interrupt Priority Level.
| Name: | SR |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| VF | CTX[2:0] | ||||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| OA | OB | SA | SB | OAB | SAB | IPL3 | |||
| Access | R/W | R/W | R/W | R/W | R | R/C | R/C | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IPL[2:0] | RA | N | OV | Z | C | ||||
| Access | R/W | R/W | R/W | R | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 23 – VF Vector (Fetch) Fail Status bit
| Value | Description |
|---|---|
1 |
Indicates to the Bus Error handler that the source of the bus error is a vector fetch. The vector data read will be substituted with the contents of the Vector Fail Address (VFA) SFR. |
0 |
Indicates to the Bus Error handler that the source of the bus error is not a vector fetch. |
Bits 18:16 – CTX[2:0] Current (W register) Context Identifier bits
| Value | Description |
|---|---|
| 111 | Context 7 is currently in use. |
| 110 | Context 6 is currently in use. |
| 101 | Context 5 is currently in use. |
| 100 | Context 4 is currently in use. |
| 011 | Context 3 is currently in use. |
| 010 | Context 2 is currently in use. |
| 001 | Context 1 is currently in use. |
| 000 | Context 0 is currently in use. |
Bit 15 – OA Accumulator A Fractional Overflow Status bit
| Value | Description |
|---|---|
1 |
Accumulator A fractional overflow has occurred (its contents can no longer be represented as a 1.31 fractional value). |
0 |
Accumulator A has not overflowed. |
Bit 14 – OB Accumulator B Fractional Overflow Status bit
| Value | Description |
|---|---|
1 |
Accumulator B fractional overflow has occurred (its contents can no longer be represented as a 1.31 fractional value). |
0 |
Accumulator B has not overflowed. |
Bit 13 – SA Accumulator A Saturation/Sign Overflow ‘Sticky’ Status bit
| Value | Description |
|---|---|
1 |
Accumulator A is saturated, or has been saturated at some time or has overflowed into bit 71 (if saturation is disabled). |
0 |
Accumulator A is not saturated or has not overflowed into bit 71 (if saturation is disabled). |
Bit 12 – SB Accumulator B Saturation/Sign Overflow ‘Sticky’ Status bit
| Value | Description |
|---|---|
1 |
Accumulator B is saturated, or has been saturated at some time or has overflowed into bit 71 (if saturation is disabled). |
0 |
Accumulator B is not saturated or has not overflowed into bit 71 (if saturation is disabled). |
Bit 11 – OAB Combined Accumulator A or Accumulator B Fractional Overflow Status bit
| Value | Description |
|---|---|
1 |
Accumulators A or B fractional overflow has occurred (one or both of their contents can no longer be represented as a 1.31 fractional value). |
0 |
Neither Accumulators A nor B have overflowed. |
Bit 10 – SAB Combined Accumulator A or Accumulator B "Sticky" Status bit
| Value | Description |
|---|---|
1 |
Accumulators A or B are saturated, or have been saturated at some time or have overflowed into bit 71 (if saturation is disabled). |
0 |
Neither Accumulator A nor B are saturated or have overflowed into bit 71 (if saturation is disabled). |
Bit 8 – IPL3 MS-bit of CPU Priority Level Nibble bit
User mode: This bit is R/C-0 (read-only if Supervisor mode supported) and will reset to 1’b0.
Supervisor mode: This bit is R/C-0 (CPU will reset into Supervisor mode).
| Value | Description |
|---|---|
| 1 | CPU Priority ≥ 8 (trap exception underway). |
| 0 | CPU Priority < 8 (no trap exception underway). |
Bits 7:5 – IPL[2:0] CPU Interrupt Priority Level status bits
User mode: This bit is R/C-0 (read-only if Supervisor mode supported) and will reset to 1’b0.
Supervisor mode: This bit is R/C-0 (CPU will reset into Supervisor mode).
| Value | Description |
|---|---|
| 111 | All interrupts disabled. |
| 110 | Level 7 interrupts enabled. |
| 101 | Level 6 and 7 interrupts enabled. |
| 100 | Level 5 through 7 interrupts enabled. |
| 011 | Level 4 through 7 interrupts enabled. |
| 010 | Level 3 through 7 interrupts enabled. |
| 001 | Level 2 through 7 interrupts enabled. |
| 000 | Level 1 through 7 interrupts enabled. |
Bit 4 – RA REPEAT Loop Active bit
| Value | Description |
|---|---|
| 1 | REPEAT loop is in progress. |
| 0 | REPEAT loop is not in progress. |
Bit 3 – N MCU ALU Negative bit
| Value | Description |
|---|---|
| 1 | Result was negative. |
| 0 | Result was not negative (zero or positive). |
Bit 2 – OV MCU ALU Overflow bit
| Value | Description |
|---|---|
| 1 | Overflow occurred for signed arithmetic (in this arithmetic operation). |
| 0 | No overflow occurred. |
Bit 1 – Z ALU ‘Sticky’ Zero bit
| Value | Description |
|---|---|
| 1 | An operation which effects the Z bit has set it at some time in the past. |
| 0 | The most recent operation which effects the Z bit has cleared it (i.e. a non-zero result). |