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High-Performance dsPIC33A Core with Floating-Point Unit, High-Speed ADCs and High-Speed PWM
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14
CAN Flexible Data-Rate (FD) Protocol Module
14.5
Modes of Operation
14.5.3
Normal Modes
Operating Conditions
High-Performance dsPIC33A DSP/CISC CPU
Memory Features
Security Features
High-Speed PWM
High-Speed Analog-to-Digital Converters
Peripheral Features
Analog Features
Safety Features
Functional Safety Support
Qualification
Programming and Debug Interfaces
dsPIC33AK512MPS512
Family Features
Pin Diagrams
Pinout I/O Descriptions
Terminology Cross Reference
1
Device Overview
2
Guidelines for Getting Started with Digital Signal Controllers
3
CPU
4
Memory Organization
5
Data Memory
6
Flash Program Memory
7
Configuration Bits
8
Security Module
9
Resets
10
Interrupt Controller
11
I/O Ports with Edge Detect
12
Oscillator Module
13
Direct Memory Access (DMA) Controller
14
CAN Flexible Data-Rate (FD) Protocol Module
14.1
Device-Specific Information
14.2
Features
14.3
CAN FD Message Frames
14.4
Register Summary
14.5
Modes of Operation
14.5.1
Mode Change
14.5.2
Configuration Mode
14.5.3
Normal Modes
14.5.3.1
Normal CAN FD Mode
14.5.3.2
Normal CAN 2.0 Mode
14.5.4
Disable Mode
14.5.5
Debug Modes
14.5.6
Low-Power Modes
14.6
Configuration
14.7
Message Transmission
14.8
Transmit Event FIFO - TEF
14.9
Message Filtering
14.10
Message Reception
14.11
FIFO Behavior
14.12
Timestamping
14.13
Interrupts
14.14
Error Handling
15
High-Resolution PWM with Fine Edge Placement
16
40 MSPS Analog-to-Digital Converter (ADC)
17
Integrated Touch Controller (ITC)
18
High-Speed Analog Comparator with Slope Compensation DAC
19
Quadrature Encoder Interface (QEI)
20
Universal Asynchronous Receiver Transmitter (UART)
21
Serial Peripheral Interface (SPI)
22
Inter-Integrated Circuit (I
2
C)
23
Single-Edge Nibble Transmission (SENT)
24
Bidirectional Serial Synchronous (BiSS) Module
25
Timers
26
Capture/Compare/PWM/Timer Modules (CCP)
27
Configurable Logic Cell (CLC)
28
Peripheral Trigger Generator (PTG)
29
32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
30
Current Bias Generator (CBG)
31
UREF Reference Output
32
Operational Amplifier (Op Amp)
33
Watchdog Timer (WDT)
34
Deadman Timer (DMT)
35
Device Power-Saving Modes
36
JTAG Interface
37
In-Circuit Debugger
38
Instruction Set Summary
39
Development Support
40
Electrical Characteristics
41
Packaging Information
42
Revision History
43
Product Identification System
Microchip Information
14.5.3 Normal Modes
