25.4.2.1 Synchronous External Clock Counter Considerations
In Synchronous External Clock Counter mode, the externally supplied clock must be half the internal system clock frequency or slower. Additionally, the external clock high and low times must be at least one full internal system clock period each for reliable operation. If the external clock glitches (positive or negative) or operates faster than half the peripheral clock, the timer may or may not increment. In no case will the timer increment faster than half the internal system clock.
When the timer is configured to increment from the synchronized external clock, the
interrupt latency will be ‘0
’, relative to the TMRx rollover (transition
from TMRx = PRx to ‘0
’). As the timer will be rolling over from a
synchronized clock, the interrupt output will be synchronous to the internal system clock
rising edge.
When TxCON.TCS = 1
, TxCON.ON = 1
, TxCON.TCKPS[1:0] ≠
00
and TxCON.TSYNC = 1
, the timer increments on the
synchronized rising edge of the prescaler output. The synchronization of the input signal
occurs with the internal system clock signal prior to the prescaler. The timer counts up to
a match value preloaded in the period register, then resets and continues. This
incrementing sequence repeats until the timer is disabled.