8.2.8 Peripheral Access Control Register 1
| Name: | PACCON1 |
| Offset: | 0x1E80 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| IOIM11CONWR | IOIM10CONWR | IOIM9CONWR | IOIM8CONWR | IOIM7CONWR | IOIM6CONWR | IOIM5CONWR | IOIM4CONWR | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| IOIM3CONWR | IOIM2CONWR | IOIM1CONWR | PCLKCONWR | BMXIRAMHWR | BMXIRAMLWR | IVTCREGWR | IVTBASEWR | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| IOIM11CONLK | IOIM10CONLK | IOIM9CONLK | IOIM8CONLK | IOIM7CONLK | IOIM6CONLK | IOIM5CONLK | IOIM4CONLK | ||
| Access | S/R | S/R | S/R | S/R | S/R | S/R | S/R | S/R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IOIM3CONLK | IOIM2CONLK | IOIM1CONLK | PCLKCONLK | BMXIRAMHLK | BMXIRAMLLK | IVTCREGLK | IVTBASELK | ||
| Access | S/R | S/R | S/R | S/R | S/R | S/R | S/R | S/R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – IOIM11CONWR IOIM 11 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 30 – IOIM10CONWR IOIM 10 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 29 – IOIM9CONWR IOIM 9 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 28 – IOIM8CONWR IOIM 8 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 27 – IOIM7CONWR IOIM 7 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 26 – IOIM6CONWR IOIM 6 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 25 – IOIM5CONWR IOIM 5 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 24 – IOIM4CONWR IOIM 4 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 23 – IOIM3CONWR IOIM 3 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 22 – IOIM2CONWR IOIM 2 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 21 – IOIM1CONWR IOIM 1 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 20 – PCLKCONWR PWM Clock Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 19 – BMXIRAMHWR BMX Instruction RAM High Address Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 18 – BMXIRAMLWR BMX Instruction RAM Low Address Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 17 – IVTCREGWR Interrupt Vector Collapse Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 16 – IVTBASEWR Interrupt Vector Base Address Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 15 – IOIM11CONLK IOIM 11 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 14 – IOIM10CONLK IOIM 10 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 13 – IOIM9CONLK IOIM 9 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 12 – IOIM8CONLK IOIM 8 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 11 – IOIM7CONLK IOIM 7 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 10 – IOIM6CONLK IOIM 6 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 9 – IOIM5CONLK IOIM 5 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 8 – IOIM4CONLK IOIM 4 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 7 – IOIM3CONLK IOIM 3 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 6 – IOIM2CONLK IOIM 2 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 5 – IOIM1CONLK IOIM 1 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 4 – PCLKCONLK PWM Clock Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 3 – BMXIRAMHLK BMX Instruction RAM High Address Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 2 – BMXIRAMLLK BMX Instruction RAM Low Address Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 1 – IVTCREGLK Interrupt Vector Collapse Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 0 – IVTBASELK Interrupt Vector Base Address Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
