8.2.2 IRT Control Register

Legend: HS = Hardware Settable bit, S = Set Only bit, R = Readable bit

Note:
  1. Register is read-only when PLCK bit is set.
  2. If PLCK bit is set then the access to IRT regions is disabled and the IRTCTRL and IRTSTAT registers are read-only.
  3. DBG bit controls debug access to the IRT partition when IRT is enabled.
  4. EAA controls the external access via debug and ICSP interfaces when IRT and secure debug are enabled. Setting of EAA bit allows debug and ICSP programmer access; otherwise, these functions are disabled.
Name: IRTCTRL
Offset: 0x2E4

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
    PLCK DONEDBGEAA 
Access R/HSR/SR/WR/W 
Reset 0000 

Bit 4 – PLCK  IRT Partition Lock Status bit (1,2)

ValueDescription
1 IRT partition is locked.
0 IRT partition is not locked.

Bit 2 – DONE UCA Write-Protect Enable bit

Write 1 to set; Writing 0 has no effect
ValueDescription
1 IRT execution is done.
0 IRT execution is not finished.

Bit 1 – DBG  IRT Debug Enable bit (3)

Reset on POR or BOR only
ValueDescription
1 Debug access to IRT partition is allowed.
0 Debug access to IRT partition is disabled.

Bit 0 – EAA  External Access (Debugger or Programmer) Enable Bit(4)

Reset on POR or BOR only
ValueDescription
1 External access for debug, programming and test interfaces is enabled.
0 External access for debug, programming and test interfaces is disabled.