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High-Performance dsPIC33A Core with Floating-Point Unit, High-Speed ADCs and High-Speed PWM
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20
Universal Asynchronous Receiver Transmitter (UART)
20.4
Operation
20.4.1
Clocking and Baud Rate Configuration
20.4.1.5
Data Bit Detection
20.4.1.5.1
Legacy Mode
Operating Conditions
High-Performance dsPIC33A DSP/CISC CPU
Memory Features
Security Features
High-Speed PWM
High-Speed Analog-to-Digital Converters
Peripheral Features
Analog Features
Safety Features
Functional Safety Support
Qualification
Programming and Debug Interfaces
dsPIC33AK512MPS512
Family Features
Pin Diagrams
Pinout I/O Descriptions
Terminology Cross Reference
1
Device Overview
2
Guidelines for Getting Started with Digital Signal Controllers
3
CPU
4
Memory Organization
5
Data Memory
6
Flash Program Memory
7
Configuration Bits
8
Security Module
9
Resets
10
Interrupt Controller
11
I/O Ports with Edge Detect
12
Oscillator Module
13
Direct Memory Access (DMA) Controller
14
CAN Flexible Data-Rate (FD) Protocol Module
15
High-Resolution PWM with Fine Edge Placement
16
40 MSPS Analog-to-Digital Converter (ADC)
17
Integrated Touch Controller (ITC)
18
High-Speed Analog Comparator with Slope Compensation DAC
19
Quadrature Encoder Interface (QEI)
20
Universal Asynchronous Receiver Transmitter (UART)
20.1
Device-Specific Information
20.2
Architectural Overview
20.3
Register Summary
20.4
Operation
20.4.1
Clocking and Baud Rate Configuration
20.4.1.1
Legacy Mode
20.4.1.2
Fractional Division Mode
20.4.1.3
UART Baud Rate Tables
20.4.1.4
Auto-Baud Feature
20.4.1.5
Data Bit Detection
20.4.1.5.1
Legacy Mode
20.4.1.5.1.1
Low-Speed Mode (CLKMOD =
0
AND BRGS =
0
)
20.4.1.5.1.2
High-Speed Mode (CLKMOD =
0
and BRGS =
1
)
20.4.1.5.2
Fractional Division Mode (CLKMOD =
1
)
20.4.2
UART Modes
20.5
Application Examples
20.6
Interrupts
20.7
Power-Saving Modes
21
Serial Peripheral Interface (SPI)
22
Inter-Integrated Circuit (I
2
C)
23
Single-Edge Nibble Transmission (SENT)
24
Bidirectional Serial Synchronous (BiSS) Module
25
Timers
26
Capture/Compare/PWM/Timer Modules (CCP)
27
Configurable Logic Cell (CLC)
28
Peripheral Trigger Generator (PTG)
29
32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
30
Current Bias Generator (CBG)
31
UREF Reference Output
32
Operational Amplifier (Op Amp)
33
Watchdog Timer (WDT)
34
Deadman Timer (DMT)
35
Device Power-Saving Modes
36
JTAG Interface
37
In-Circuit Debugger
38
Instruction Set Summary
39
Development Support
40
Electrical Characteristics
41
Packaging Information
42
Revision History
43
Product Identification System
Microchip Information
20.4.1.5.1 Legacy Mode
