15.4.3.8 Override

The override feature can be used to take control of the PWM outputs and force certain conditions onto the pins. User software can override the output states of the pins by writing a ‘1’ to the OVRENH and OVRENL control bits located in the PGxIOCON2 register. The state of the pins, when overridden, will be that of the value written to OVRDAT[1:0], unless it conflicts with restrictions imposed by the given Output mode. Most constraints are in Complementary mode and are discussed in Complementary Output Mode.

The OVRDAT[1:0] and OVRENH/L control bits are double-buffered for flexibility. The OSYNC[1:0] control bits in the PGxIOCON2 register specify when the user override values are applied to the PWM outputs. Manual software overrides can be applied at the following times:

  • At the start of a new PWM cycle
  • Immediately (or as soon as possible)
  • As configured by the UPDMOD[2:0] control bits (see Data Buffering).

Synchronizing overrides on multiple PG is done by enabling one of the Host/Client modes as defined by UPDMOD bits.

Like data updates, overrides are applied by a write of the UPDREQ. When UPDATE = 0, the user software may write new values to OVRENx or OVRDAT to set the UPDREQ bit. Setting the UPDREQ bit ‘commits’ the new values to the PWM Generator. The UPDATE bit will set, and writes are prohibited. When the process is complete, the UPDATE bit is cleared by hardware.

In general, SOC Update modes are recommend as they allow scheduling of override updates with an interrupt, which provides the maximum time to complete the next write. Otherwise the UPDATE bit should be polled to write at a safe time.

Override update process:

  1. Configure OSYNC and UPDMOD as needed for application.
  2. Configure PWM interrupt for SOC (default).
  3. When interrupt event occurs:
    1. Read UPDATE bit and verify it is '0'.
    2. Write new values to OVRENx or OVRDAT.
    3. Set UPDREQ bit to a '1' to commit data to PWM buffer.
Synchronizing Multiple PWM Generator override updates:
  1. Configure host PG for SOC updates by writing OSYNC = '0' and MSTEN = '1'.
  2. Configure client(s) PG for 'Client SOC' mode by writing OSYNC = 0b10 and UPDMOD = 0b0101.
  3. Configure host PWM interrupt for SOC (default).
  4. When interrupt event occurs:
    1. Read host UPDATE bit and verify it is '0'.
    2. Host write new data values to OVRENx or OVRDAT for all PWM generators (PGx).
    3. Set host UPDREQ bit to a '1' to commit data to PWM buffer.

On the next SOC, all PWM generators configured as clients will operate with new data values.