15.4.3.10 Data Buffering

The PWM module allows for certain SFR data values to be buffered and applied to the PWM output at later events. The following user registers and/or bits are buffered, allowing the user to modify data while the PWM Generator operates on the previous set of data values:

  • MPER
  • MDC
  • MPHASE
  • PGxPER
  • PGxPHASE
  • PGxDC
  • PGxTRIGA
  • PGxTRIGB
  • PGxTRIGC
  • PGxDT
  • SWAP
  • OVRDAT[1:0] (software output override values)
  • OVREN (software output override enables)

Data are transferred from the SFR registers to the internal PWM registers at the start of a PWM cycle. This can be every one, two or four timer cycles, depending on the PWM Generator mode and the Output mode. It may be required that a register be updated immediately to produce an immediate change in a power converter operation. In other cases, it may be desirable to hold off the buffer update until some external event occurs where data coherency between multiple PWM Generators is of concern. The module supports the user to specify when the contents of the SFRs associated with a PWM Generator are transferred into the “active” internal registers. Available options are:

  • Immediately
  • At the beginning of the next PWM cycle
  • As part of a larger group

The UPMOD[2:0] control bits in the PGxCON register determine the Operating mode for register updates. The UPDATE status bit in the PGxSTAT register allows visibility to when register updates are complete, and changes may be applied. When UPDATE = 0, the user software may write new values to the PWM Data registers and set the UPDREQ bit when done. Setting the UPDREQ bit ‘commits’ the new values to the PWM Generator, and user software can not modify PWM data values until the bit is cleared by hardware.

In general, SOC Update modes are recommended as they allow scheduling of override updates with an interrupt, which provides the maximum time to complete the next write. Otherwise the UPDATE bit should be polled to write at a safe time.

Data update process:

  1. Configure UPDMOD as needed for application.
  2. Configure PWM interrupt for SOC (default).
  3. When interrupt event occurs:
    1. Read UPDATE bit and verify it is '0'.
    2. Write new data value(s).
    3. Set UPDREQ bit to a '1' to commit data to PWM buffer.

On the next SOC, the PWM Generator will operate with new data values.

In order to avoid extra CPU cycles, the data updates can be configured to be automatically performed on a write to one of the PWM Data registers. The register is selected using the UPDTRG[1:0] bits in the PGxEVT1 control register. The default selection is that the UPDREQ bit must be manually set in software. A write to the PGxDC register can trigger an update, since many applications frequently change the duty cycle of the PWM. The PGxPHASE and PGxTRIGA registers may also be chosen as update triggers. These registers may be modified on a frequent basis in variable phase applications. The register that is selected as the update trigger must be the last one to be written if several PWM Data registers are to be updated. The PWM Data registers should not be modified once the UPDATE bit becomes set. User software must wait for the PWM hardware to clear the UPDATE bit before the Data registers can be modified again.