15.4.3.11 Time Base Capture

A time base capture feature is provided as the PWM timer itself is not directly readable. When the timer value is needed by the application, it may be captured and read via the PGxCAP register. The capture feature is gated with the CAPEN (PGxIOCON1[23]) bit. In a Default state of '0', it will only capture one event until the contents of PGxCAP are read, regardless of subsequent capture triggers. With CAPEN is set to '1', subsequent capture triggers will overwrite the PGxCAP register. There are two methods to trigger an event: either manually with software or with hardware on a PCI event. The CAPSRC[2:0] control bits (PGxIOCON1[22:20]) are used to select either a manual capture or one of the four PCI blocks as the trigger for a time base capture.

To manually capture the timer value, write a ‘1’ to PGxCAP[0]. The CAP status bit (PGxSTAT[5]) will set to indicate the capture is complete, and then the user may read the PGxCAP register to determine the time base value at the time of the hardware event. A read operation of PGxCAP will clear the CAP status bit. It is recommended to read the CAP status bit to verify it is set before reading PGxCAP. This is to avoid a read of the PGxCAP register at the same time as the PWM hardware is writing it. An alternative method is to schedule reads with an interrupt to avoid concurrent access.

There will be up to three time base clock cycles of latency between the time of the actual event that caused the capture and the actual time base value that is captured. This delay is due to synchronization and sampling delays.