15.4.3.5 PWM Control Input (PCI) Logic Blocks

The PWM Control Input (PCI) Logic blocks are flexible state machines that can be used for a wide variety of purposes. The PCI blocks condition input signals and provide output signals used to trigger, gate and override the PWM outputs. The PCI also allows PWM Generators to interface with one another and external input signals. The PCI blocks can be used to implement output control and trigger algorithms in hardware instead of using software resources. There are four identical PCI blocks available for each PWM Generator. The PCI blocks are:

  • Faultx (where x = 1,2)
  • Current Limit
  • Feed-Forward
  • Sync

The names of the PCI block do not limit their usage; they are given unique names to designate the priority levels. The Sync PCI block is intended for triggering, specifically from external events, including other PWM Generators. The Fault, Current Limit and Feed-Forward PCI blocks are used to control the PWM output from external signals and other peripherals. The output state of the PWM pins can be independently configured to a predefined state for each PCI block, and it operates in a priority scheme if more than one PCI block requests control over the PWM outputs. Each PCI block has its own control register, PGxyPCI (with y = F, CL, FF or S), that contains the control bit associated with its operation. The PCI logic has three major components used to create logic functions:

  • Inputs:
    • PCI source
    • PCI source qualifier, used to gate the PCI source signal
    • Terminator event, used to stop the ‘PCI_active’ output signal
    • Terminator qualifier event, used to gate the terminator event
  • Acceptance logic
  • Output and bypass function

Typical PCI source signals may include:

  • Outputs to other PWM Generators
  • Combo triggers (see Combinatorial Triggers)
  • Analog-to-Digital Converter (ADC)
  • Analog comparator
  • Input capture
  • Configurable Logic Cell (CLC)
  • External input (device pin)

The output of a PCI block (PCI_active signal) is made available to the PWM output logic and other PWM Generators. The status of the output signal of each PCI block is made available in the PGxSTAT register in both current and latched states. The PCI blocks can also generate interrupts (see Event Interrupts for more information). The block diagrams of the PCI function are shown in Figure 15-20 and Figure 15-21.

PCI Sync events will be synchronized into the PWM clock domain prior to use as a PWM Generator trigger event. Because of the synchronization, there will be some uncertainty in the time of the actual trigger event. PCI events that control the state of the output pins should be asynchronous, with some exceptions. This is because PCI events are commonly used to drive PWM pins inactive in the event of a current or voltage fault. The objective is to place the PWM pins in a known state as quickly as possible.

When the PCI event drives a PWM pin to the Active state and the dead-time generator is in use, a PCI event signal synchronized to the PWM clock domain should be used. This will ensure proper edge detection by the dead-time logic. PWM pins should be driven inactive asynchronously by the PCI event signal when the dead-time generator is enabled for the reasons stated in this section.

Figure 15-20. PCI Function Block Diagram
Figure 15-21. PCI Acceptance Modes