15.4.44 Auxiliary PWM Master Duty Cycle Register

Note:

These bits cannot be modified while UPDATE = 1.

Name:	AMDC
Offset:	0x1410


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					MDC[19:16]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8
	MDC[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	MDC[7:4]
Access	R/W	R/W	R/W	R/W
Reset	0	0	0	0

Bits 19:4 – MDC[19:4] Master Duty Cycle Register bits⁽¹⁾

This register holds the duty cycle value that can be shared by multiple PWM Generators.

Note: Duty cycle values less than 0x0010 should not be used.

DS70005591D

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