15.4.14 PWM Generator x I/O Control 2 Register

Note:
  1. This bit is applied to operation in Complementary mode only. When the outputs are swapped, the priority is observed based on Figure 15-15.
  2. The PWM PGx FRZ bits are controlled using MPLAB IDE. To access the peripheral FRZ bit, go to Project Properties and open the options for the debugger (for example, ICDx). Select Freeze Peripherals from the option categories drop down menu, then select the PWM PGx instance. By default, the FRZ bit is set when Debug mode is entered.
Name: PGxIOCON2
Offset: 0x105C, 0x10D0, 0x1144, 0x11B8, 0x122C, 0x12A0, 0x1314, 0x1388

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 CLMOD OVRENHOVRENL     
Access R/WR/WR/W 
Reset 000 
Bit 15141312111098 
   OVRDAT[1:0]OSYNC[1:0]FLT2DAT[1:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
 FLT1DAT[1:0]CLDAT[1:0]FFDAT[1:0]DBDAT[1:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 23 – CLMOD  Current Limit Mode Select bit(1)

ValueDescription
1

If PCI current limit is active, then the PWMxH and PWMxL output signals are inverted (bit flipping), and the CLDAT[1:0] bits are not used.
0

If PCI current limit is active, then the CLDAT[1:0] bits define the PWM output levels.

Bit 21 – OVRENH User Override Enable for PWMxH Pin bit

ValueDescription
1

OVRDAT[1] provides data for output on the PWMxH pin.
0

PWM Generator provides data for the PWMxH pin.

Bit 20 – OVRENL User Override Enable for PWMxL Pin bit

ValueDescription
1

OVRDAT[0] provides data for output on the PWMxL pin.
0

PWM Generator provides data for the PWMxL pin.

Bits 13:12 – OVRDAT[1:0] Data for PWMxH/PWMxL Pins if Override is Enabled bits

Description

If OVRENH = 1, then OVRDAT[1] provides data for PWMxH.

If OVRENL = 1, then OVRDAT[0] provides data for PWMxL.

Bits 11:10 – OSYNC[1:0] User Output Override Synchronization Control bits

ValueDescription
11 User output overrides via the SWAP, OVRENL/H and OVRDAT[1:0] bits are synchronized to the data buffer update of the selected PWM mode. This makes this setting equivalent to setting 10 when UPDMOD[2:0] = 000 with UPDREQ properly set manually.
10

User output overrides via the SWAP, OVRENL/H and OVRDAT[1:0] bits occur when specified by the UPMOD[2:0] bits in the PGxCON register.
01

User output overrides via the SWAP, OVRENL/H and OVRDAT[1:0] bits occur immediately (as soon as possible).
00

User output overrides via the SWAP, OVRENL/H and OVRDAT[1:0] bits are synchronized to the local PWM time base (next start of cycle).

Bits 9:8 – FLT2DAT[1:0] Data for PWMxH/PWMxL Pins if FLT Event is Active bits

Description

If Fault is active, then FLTDAT[1] provides data for PWMxH.

If Fault is active, then FLTDAT[0] provides data for PWMxL.

Bits 7:6 – FLT1DAT[1:0] Data for PWMxH/PWMxL Pins if FLT Event is Active bits

Description

If Fault is active, then FLTDAT[1] provides data for PWMxH.

If Fault is active, then FLTDAT[0] provides data for PWMxL.

Bits 5:4 – CLDAT[1:0] Data for PWMxH/PWMxL Pins if CLMT Event is Active bits

Description

If current limit is active, then CLDAT[1] provides data for PWMxH.

If current limit is active, then CLDAT[0] provides data for PWMxL.

Bits 3:2 – FFDAT[1:0] Data for PWMxH/PWMxL Pins if Feed-Forward Event is Active bits

Description

If feed-forward is active, then FFDAT[1] provides data for PWMxH.

If feed-forward is active, then FFDAT[0] provides data for PWMxL.

Bits 1:0 – DBDAT[1:0]  Data for PWMxH/PWMxL Pins if Debug Mode is Active bits(2)

Description

If Debug mode is active and Freeze Peripherals is selected in the MPLAB IDE Project Properties, then DBDAT[1] provides data for PWMxH.

If Debug mode is active and Freeze Peripherals is selected in the MPLAB IDE Project Properties, then DBDAT[0] provides data for PWMxL.