1.3.3.2 CORETSE_0

The CORETSE_0 (CoreTSE) block is used to implement the Ethernet MAC. This block is configured in the Ten-bit Interface (TBI) mode to interface with the VSC PHY using the SGMII interface, as shown in the following figure. The MDIO PHY Address value is used by the Mi-V soft processor to read and write to the management registers of the CoreTSE IP. The Include receive slip logic check box is not selected because the CoreTSE IP has a built-in word alignment logic in TBI mode.