AN4623

1.3.3.7 PF_CCC_0

PF_CCC_0 (PolarFire Clock Conditioning Circuitry) generates the fabric reference clock that drives the soft processor and the APB peripherals (CoreTSE and CoreSPI). The PF_CCC_0 IP is configured to generate one output fabric clock from an on-board 50 MHz crystal oscillator.

The following figure shows the PF_CCC_0 input clock configuration.

Figure 1-7. PF_CCC_0 Input Clock Configuration

The following figure shows the PF_CCC_0 output clock configuration. This design uses an 80 MHz system clock for configuring the APB peripherals.

Figure 1-8. PF_CCC_0 Output Clock Configuration

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.