1.3.3.12 CoreAPB3
(Ask a Question)CoreAPB3 is configured as per the following figure to connect the peripherals CoreTSE, CoreSPI, and CoreUARTapb as slaves.
CoreAPB3 is configured as follows:
- APB Master Data Bus Width: 32-bit
- Number of address bits driven by master: 16. The Mi-V processor addresses slaves using 16-bit addressing, so the final address for these slaves translates to 0x6000_0000, 0x6000_1000, and 0x6000_2000
- Enabled APB Slave Slots: S0, S1, and S2 (for CoreTSE, CoreUARTapb, and CoreSPI,
respectively).
Figure 1-12. CoreAPB3 Configuration 