1.3.3.8 PF_IOD_CDR_CCC_C0
(Ask a Question)The PF_IOD_CDR_CCC IP used for generating high-speed bank clocks for PF_IOD_CDR. This IP is in PLL-DLL cascaded mode to generate high-speed bank clocks of four phases: 0, 90, 180, and 270 from a 125 MHz input. CDR requires four phases of HS_IO_CLK running at half the frequency of the serial data rate. Therefore, the HSIO clock frequency is selected as 625 MHz with four phases.
PF_IOD_CDR_CCC also generates the fabric Tx interface clock (TX_CLK_G) for the CoreTSE block by dividing the bank clock by the ratio of 5. The Delay-Locked Loops (DLL) are needed to control the clock position (delay) with DLL codes when the data is active on the Rx interface (RX_P/RX_N). A glitch-less DLL can adjust the clock delay setting when the data is active.
The following figure shows the PF_IOD_CCC_C0_0 configuration.
