1.3.3.1 PF_IOD_CDR_C0_0
(Ask a Question)The PF_IOD_CDR_C0_0 (PF_IOD_CDR) block is configured for 1250 Mbps. The data rate is set to 1250 Mbps because the SGMII interface operates at this speed. The Enable BITSLIP port check box is not selected because the CoreTSE IP has a built-in word alignment logic. The following figure shows the configuration of the PF_IOD_CDR_C0 block.
The Advanced tab includes the Jump step size option that specifies the precision of the clock adjustment during clock recovery. The supported step sizes are: 2 or 3; this demo uses a step size of 3.