4.8.11.6 SSMSR – SSM Status Register
| Name: | SSMSR |
| Offset: | 0x0E6 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | SSMERR | | | | SSMESM[3:0] | |
| Access | R/W | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – SSMERR SSM Error
This bit is set to ‘1’ if the SSM stops operation with an error condition, such as when a sub-state machine is waiting for a condition and the predefined time is over. The flag can be reset by writing a ‘1’ to this bit.
Bit 6 – Reserved Bit
This bit is reserved and read as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read as ‘0’.
Bits 3:0 – SSMESM[3:0] SSM Error State Machine
This value holds the number of the state
machine that raised the most recent error. Possible candidates for error are PLL
enable, PLL lock and get telegram state machines. See Sub-state Machine
Selection in the MSMCR1 from Related Links.
