4.8.11.1 SSMCR – SSM Control Register
Several options can be selected in the control register for how the chip is initialized by the state machines.| Name: | SSMCR |
| Offset: | 0x0E2 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | SETRPB | SETRPA | | | | | SSMTM | | |
| Access | R/W | R/W | R | R | R | R | R/W | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – SETRPB SSM Enable Transparent Path B
If this bit is set, the transparent receive path B output is automatically enabled and disabled by the SSM.
Bit 6 – SETRPA SSM Enable Transparent Path A
If this bit is set, the transparent receive path A output is automatically enabled and disabled by the SSM.
Bit 5 – Reserved bit
This bit is reserved and read as ‘0’.
Bit 4 – Reserved bit
This bit is reserved and read as ‘0’.
Bit 3 – Reserved bit
This bit is reserved and read as ‘0’.
Bit 2 – Reserved bit
This bit is reserved and read as ‘0’.
Bit 1 – SSMTM SSM Temperature Measurement
This bit configures the Start-up mode for temperature measurement.
Bit 0 – Reserved bit
This bit is reserved and read as ‘0’.
