4.8.11.13 MSMCR2 – Host State Machine Control Register 2
| Name: | MSMCR2 |
| Offset: | 0x0ED |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MSMSM3[3:0] | MSMSM2[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:4 – MSMSM3[3:0] Host State Machine (Sub)State Machine Select 3
Bits 3:0 – MSMSM2[3:0] Host State Machine (Sub)State Machine Select 2
Note: For more details on
configuration, see Sub-state Machine Selection in the MSMCR1 from
Related Links.