2.6.1 Instruction Set Summary

The processor implements a version of the Thumb instruction set. The following table lists the supported instructions.

In the following table:

angle brackets, <>, enclose alternative forms of the operand
braces, {}, enclose optional operands
the Operands column is not exhaustive
Op2 is a flexible second operand that can be either a register or a constant
most instructions can use an optional condition code suffix.

For more information on the instructions and operands, see the instruction descriptions.

Table 2-20. Cortex-M3 Processor Instructions
Mnemonic	Operands	Brief description	Flags
ADC, ADCS	{Rd,} Rn, Op2	Add with Carry	N, Z, C, V
ADD, ADDS	{Rd,} Rn, Op2	Add	N, Z, C, V
ADD, ADDW	{Rd,} Rn, #imm12	Add	N, Z, C, V
ADR	Rd, label	Load PC-relative Address	—
AND, ANDS	{Rd,} Rn, Op2	Logical AND	N, Z, C
ASR, ASRS	Rd, Rm, <Rs\|#n>	Arithmetic Shift Right	N, Z, C
B	label	Branch	—
BFC	Rd, #lsb, #width	Bit Field Clear	—
BFI	Rd, Rn, #lsb, #width	Bit Field Insert	—
BIC, BICS	{Rd,} Rn, Op2	Bit Clear	N, Z, C
BKPT	#imm	Breakpoint	—
BL	label	Branch with Link	—
BLX	Rm	Branch indirect with Link	—
BX	Rm	Branch indirect	—
CBNZ	Rn, label	Compare and Branch if Non Zero
CBZ	Rn, label	Compare and Branch if Zero	—
CLREX		Clear Exclusive	—
CLZ	Rd, Rm	Count Leading Zeros	—
CMN	Rn, Op2	Compare Negative	N, Z, C, V
CMP	Rn, Op2	Compare	N, Z, C, V
CPSID	i	Change Processor State, Disable Interrupts	—
CPSIE	i	Change Processor State, Enable Interrupts	—
DMB		Data Memory Barrier	—
DSB		Data Synchronization Barrier	—
EOR, EORS	{Rd,} Rn, Op2	Exclusive OR	N, Z, C
ISB		Instruction Synchronization Barrier	—
IT		If-Then condition block	—
LDM	Rn{!}, reglist	Load Multiple registers, increment after	—
LDMDB, LDMEA	Rn{!}, reglist	Load Multiple registers, decrement before	—
LDMFD, LDMIA	Rn{!}, reglist	Load Multiple registers, increment after	—
LDR	Rt, [Rn, #offset]	Load Register with word	—
LDRB, LDRBT	Rt, [Rn, #offset]	Load Register with byte	—
LDRD	Rt, Rt2, [Rn, #offset]	Load Register with two bytes	—
LDREX	Rt, [Rn, #offset]	Load Register Exclusive
LDREXB	Rt, [Rn]	Load Register Exclusive with Byte	—
LDREXH	Rt, [Rn]	Load Register Exclusive with Halfword	—
LDRH, LDRHT	Rt, [Rn, #offset]	Load Register with Halfword	—
LDRSB, LDRSBT	Rt, [Rn, #offset]	Load Register with Signed Byte	—
LDRSH, LDRSHT	Rt, [Rn, #offset]	Load Register with Signed Halfword	—
LDRT	Rt, [Rn, #offset]	Load Register with word	—
LSL, LSLS	Rd, Rm, <Rs\|#n>	Logical Shift Left	N, Z, C
LSR, LSRS	Rd, Rm, <Rs\|#n>	Logical Shift Right	N, Z, C
MLA	Rd, Rn, Rm, Ra	Multiply with Accumulate, 32-bit result	—
MLS	Rd, Rn, Rm, Ra	Multiply and Subtract, 32-bit result	—
MOV, MOVS	Rd, Op2	Move	N, Z, C
MOVT	Rd, #imm16	Move Top	—
MOVW, MOV	Rd, #imm16	Move 16-bit constant	N, Z, C
MRS	Rd, spec_reg	Move from Special Register to general register	—
MSR	spec_reg, Rm	Move from general register to Special Register	N, Z, C,V
MUL, MULS	{Rd,} Rn, Rm	Multiply, 32-bit result	N, Z
MVN, MVNS	Rd, Op2	Move NOT	N, Z, C
NOP		No Operation	—
ORN, ORNS	{Rd,} Rn, Op2	Logical OR NOT	N, Z, C
ORR, ORRS	{Rd,} Rn, Op2	Logical OR	N, Z, C
POP	reglist	Pop registers from stack	—
PUSH	reglist	Push registers onto stack	—
RBIT	Rd, Rn	Reverse Bits	—
REV	Rd, Rn	Reverse byte order in a word	—
REV16	Rd, Rn	Reverse byte order in each halfword	—
REVSH	Rd, Rn	Reverse byte order in bottom halfword and sign extend	—
ROR, RORS	Rd, Rm, <Rs\|#n>	Rotate Right	N, Z, C
RRX, RRXS	Rd, Rm	Rotate Right with Extend	N, Z, C
RSB, RSBS	{Rd,} Rn, Op2	Reverse Subtract	N, Z, C, V
SBC, SBCS	{Rd,} Rn, Op2	Subtract with Carry	N, Z, C, V
SBFX	Rd, Rn, #lsb, #width	Signed Bit Field Extract	—
SDIV	{Rd,} Rn, Rm	Signed Divide	—
SEV		Send Event	—
SMLAL	RdLo, RdHi, Rn, Rm	Signed Multiply with Accumulate (32 x 32 + 64), 64-bit result	—
SMULL	RdLo, RdHi, Rn, Rm	Signed Multiply (32 x 32), 64-bit result	—
SSAT	Rd, #n, Rm {,shift #s}	Signed Saturate	Q
STM	Rn{!}, reglist	Store Multiple registers, increment after	—
STMDB, STMEA	Rn{!}, reglist	Store Multiple registers, decrement before	—
STMFD, STMIA	Rn{!}, reglist	Store Multiple registers, increment after	—
STR	Rt, [Rn, #offset]	Store Register word	—
STRB, STRBT	Rt, [Rn, #offset]	Store Register byte	—
STRD	Rt, Rt2, [Rn, #offset]	Store Register two words	—
STREX	Rd, Rt, [Rn, #offset]	Store Register Exclusive
STREXB	Rd, Rt, [Rn]	Store Register Exclusive Byte	—
STREXH	Rd, Rt, [Rn]	Store Register Exclusive Halfword	—
STRH, STRHT	Rt, [Rn, #offset]	Store Register Halfword	—
STRT	Rt, [Rn, #offset]	Store Register word	—
SUB, SUBS	{Rd,} Rn, Op2	Subtract	N, Z, C, V
SUB, SUBW	{Rd,} Rn, #imm12	Subtract	N, Z, C, V
SVC	#imm	Supervisor Call	—
SXTB	{Rd,} Rm {,ROR #n}	Sign extend a byte	—
SXTH	{Rd,} Rm {,ROR #n}	Sign extend a halfword	—
TBB	[Rn, Rm]	Table Branch Byte	—
TBH	[Rn, Rm, LSL #1]	Table Branch Halfword	—
TEQ	Rn, Op2	Test Equivalence	N, Z, C
TST	Rn, Op2	Test	N, Z, C
UBFX	Rd, Rn, #lsb, #width	Unsigned Bit Field Extract	—
UDIV	{Rd,} Rn, Rm	Unsigned Divide	—
UMLAL	RdLo, RdHi, Rn, Rm	Unsigned Multiply with Accumulate (32 x 32 + 64), 64-bit result	—
UMULL	RdLo, RdHi, Rn, Rm	Unsigned Multiply (32 x 32), 64-bit result	—
USAT	Rd, #n, Rm {,shift #s}	Unsigned Saturate	Q
UXTB	{Rd,} Rm {,ROR #n}	Zero extend a Byte	—
UXTH	{Rd,} Rm {,ROR #n}	Zero extend a Halfword	—
WFE		Wait for Event	—
WFI		Wait for Interrupt	—