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SmartFusion 2 Microcontroller Subsystem
SmartFusion 2 Microcontroller Subsystem
  1. Home
  2. 2 Cortex-M3 Processor (Reference Material)
  3. 2.6 Cortex-M3 Processor Instruction Set
  4. 2.6.9 Branch and Control Instructions

  • Introduction
  • 1 Cortex-M3 Processor Overview and Debug Features
  • 2 Cortex-M3 Processor (Reference Material)
    • 2.1 System Level Interface
    • 2.2 Integrated Configurable Debug
    • 2.3 Cortex-M3 Processor Features and Benefits Summary
    • 2.4 Cortex-M3 Processor Core Peripherals
    • 2.5 Cortex-M3 Processor Description
    • 2.6 Cortex-M3 Processor Instruction Set
      • 2.6.1 Instruction Set Summary
      • 2.6.2 CMSIS Functions
      • 2.6.3 About the Instruction Descriptions
      • 2.6.4 Memory Access Instructions
      • 2.6.5 General Data processing instructions
      • 2.6.6 Multiply and Divide Instructions
      • 2.6.7 Saturating Instructions
      • 2.6.8 Bitfield instructions
      • 2.6.9 Branch and Control Instructions
        • 2.6.9.1 B, BL, BX, and BLX
        • 2.6.9.2 CBZ and CBNZ
        • 2.6.9.3 IT
        • 2.6.9.4 TBB and TBH
      • 2.6.10 Miscellaneous Instructions
    • 2.7 Cortex-M3 Processor Peripherals
  • 3 Cache Controller
  • 4 Embedded NVM (eNVM) Controllers
  • 5 Embedded SRAM (eSRAM) Controllers
  • 6 AHB Bus Matrix
  • 7 High Performance DMA Controller
  • 8 Peripheral DMA
  • 9 Universal Serial Bus On-The-Go Controller
  • 10 Ethernet MAC
  • 11 CAN Controller
  • 12 MMUART Peripherals
  • 13 Serial Peripheral Interface Controller
  • 14 Inter-Integrated Circuit Peripherals
  • 15 MSS GPIO
  • 16 Communication Block
  • 17 RTC System
  • 18 System Timer
  • 19 Watchdog Timer
  • 20 Reset Controller
  • 21 System Register Block
  • 22 Fabric Interface Interrupt Controller
  • 23 Fabric Interface Controller
  • 24 APB Configuration Interface
  • 25 Error Detection and Correction Controllers
  • 26 Revision History
  • Microchip FPGA Support
  • Microchip Information

2.6.9 Branch and Control Instructions

The following table lists the branch and control instructions:

Table 2-30. Branch and Control Instructions
MnemonicBrief descriptionSee
BBranchB, BL, BX, and BLX
BLBranch with LinkB, BL, BX, and BLX
BLXBranch indirect with LinkB, BL, BX, and BLX
BXBranch indirectB, BL, BX, and BLX
CBNZCompare and Branch if Non ZeroCBZ and CBNZ
CBZCompare and Branch if ZeroCBZ and CBNZ
ITIf-ThenIT
TBBTable Branch ByteTBB and TBH
TBHTable Branch HalfwordTBB and TBH

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