2.6.10 Miscellaneous Instructions
The following table lists the remaining Cortex-M3 processor instructions:
| Mnemonic | Brief Description | See |
|---|---|---|
| BKPT | Breakpoint | 2.6.10.1 BKPT |
| CPSID | Change Processor State, Disable Interrupts | 2.6.10.2 CPS |
| CPSIE | Change Processor State, Enable Interrupts | 2.6.10.2 CPS |
| DMB | Data Memory Barrier | 2.6.10.3 DMB |
| DSB | Data Synchronization Barrier | 2.6.10.4 DSB |
| ISB | Instruction Synchronization Barrier | 2.6.10.5 ISB |
| MRS | Move from special register to register | 2.6.10.6 MRS |
| MSR | Move from register to special register | 2.6.10.7 MSR |
| NOP | No Operation | 2.6.10.8 NOP |
| SEV | Send Event | 2.6.10.9 SEV |
| SVC | Supervisor Call | 2.6.10.10 SVC |
| WFE | Wait For Event | 2.6.10.11 WFE |
| WFI | Wait For Interrupt | 2.6.10.12 WFI |