17.4.3 Control Register
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| 10 | Updated | R/W | 0 | This bit goes High every time the RTC updates the RTC value. It is cleared by writing '1' to the bit. It allows the CPU to know that the RTC value is stable and will not change for the next second. |
| 9 | Wakeup_set | W | 0 | Writing a '1' to this bit asserts the RTC_WAKEUP output and sets the Wakeup status bit. |
| 8 | Wakeup | R | 0 | This bit is set every time a match occurs. It is cleared by writing a '1'. Once cleared, it will not be set again until the next wakeup occurs. When WAKE_CONTINUE = 0, writing a '1' to this bit restarts the RTC counting after a wake-up occurs. |
| Wakeup_clear | W | |||
| 7 | Match | R | 0 | The RTC value matches the wakeup value. It indicates the value of the RTC_MATCH output. This is normally active for 1 second while the current time matches the alarm setting. |
| 6 | Download | W | 0 | Writing a '1' causes the current RTC value to be downloaded to the date/time upload registers initializing the upload value to the current time. This does not require any synchronization and takes place immediately. |
| 5 | Upload | R/W | 0 | When '1' is written, the date/time value loaded into the date/time registers is uploaded to the RTC and stays asserted until the internal synchronizers complete the upload. |
| 4 | Reset | W | 0 | When '1' is written, the date/time value is reset and uploaded to the RTC. This causes the upload bit to be set while the time is reset. |
| 3 | Alarm_off | W | 0 | When '1' is written, the Alarm is disabled. When it is read, it indicates that the Alarm is enabled. It reads back '1' until the internal synchronization completes and the Alarm is fully disabled. |
| Alarm_enabled | R | 0 | ||
| 2 | Alarm_on | W | 0 | When '1' is written, the Alarm is enabled. When it is read, it indicates that the Alarm is enabled. It reads back '1' as soon as the bit is written. |
| Alarm_enabled | R | 0 | ||
| 1 | Stop | W | 0 | When '1' is written, the RTC counter stops. When it is read, it indicates that the RTC is running. It reads back as '1' until the internal synchronization completes and the RTC is fully stopped. |
| Running | R | 0 | ||
| 0 | Start | W | 0 | When '1' is written, the RTC starts. When it is read, it indicates that the RTC is running. It reads back '1' as soon as the start bit is written. |
| Running | R | 0 |