17.4.6 Alarm and Compare Registers
These registers may be written when the RTC is running, but the Alarm must be disabled; the control register bit 2 reads as a '0'.
| Address Offset | Register Name | Bit Numbers | Name | R/W | Reset Value | Description |
|---|---|---|---|---|---|---|
| 0x0C | Alarm | [31:0] | Alarm Lower | R/W | 0 | Sets the alarm (wake-up) time on write and returns the alarm time on read. |
| 0x10 | [31:0] | Alarm Upper | R/W | 0 | Sets the alarm (wake-up) time on write and returns the alarm time on read. | |
| 0x14 | Compare | [31:0] | Compare Lower | R/W | 0 | Sets the compare bits on the alarm time on write and returns the compare value on read. 0: Bit is ignored 1: Bit is compared |
| 0x18 | [31:0] | Compare Upper | R/W | 0 | Sets the compare bits on the alarm time on write and returns the compare value on read. 0: Bit is ignored 1: Bit is compared |
See Table 17-5 for register bit allocation.
The Alarm setting must be set such that the ALARM*PRESCALER is greater than the 8 RTC clock cycles, assuming that the CPU writes to the control register to clear a wakeup condition within two RTC clock periods. As the prescaler value should be set to achieve a 1 Hz pulse and the slowest RTCCLK source is 32 KHz, this requirement is always true.