10.3 TSEMAC PHY Interfaces

This section describes the MII, GMII, and TBI fabric PHY interfaces. The PHY interfaces are routed to the fabric onto MSIOs in case of MII, GMII, and SerDes I/Os in case of TBI. To implement the other PHY protocols within the fabric such as RMII, RGMII, RTBI, RevMII, and SMII, these PHY protocols may be derived from appropriate wrappers implemented in fabric, which converts PHY interface signals input to the FPGA fabric as shown in Figure 10-1. The EMAC can be configured through Libero® SoC MSS configurator by selecting the interface, line speed, and enabling the management interface PHY interface. On reset, MSS Ethernet MAC turns the auto-negotiate of the Ethernet PHY to OFF. Due to difference in protocol between MSS Ethernet MAC and Ethernet PHY, user has to handle the Ethernet PHY auto-negotiation through PHY driver code. The SGMII can be implemented by means of configuring the EMAC for the TBI operation. Figure 10-2 shows TBI pins are routed to SerDes, which is configured for EPCS mode to provide SGMII functionality.

The following tables list the port names, port groups, and direction information for the default supported MII, GMII, and TBI PHY interfaces. 

Table 10-1. MII Ports
Port Name Port Group Direction Description
MII_TXD[3:0] MAC_MII_FABRIC Out Indicates MII transmit data
MII_TX_EN MAC_MII_FABRIC Out Indicates MII transmit data enable
MII_TX_ER MAC_MII_FABRIC Out Indicates MII transmit data error
MII_RXD[3:0] MAC_MII_FABRIC In Indicates MII receive data
MII_RX_ER MAC_MII_FABRIC In Indicates MII receive data error
MII_RX_DV MAC_MII_FABRIC In Indicates MII receive data valid
MII_CRS MAC_MII_FABRIC In Asynchronous carrier sense signal. Indicates at least one physical device transmits on the medium.
MII_COL MAC_MII_FABRIC In Asynchronous collision sense signal. Indicates more than one physical device transmits simultaneously on the medium.
MII_RX_CLK MAC_MII_FABRIC In Indicates MII receive clock. 25 MHz for 100 Mbps mode and 
2.5 MHz for 10 Mbps mode.
MII_RX_CLK MAC_MII_FABRIC In Indicates MII management transmit clock. 25 MHz for 100-Mbps mode and 2.5 MHz for 10 Mbps mode. MIII_TXD, MII_TX_EN, MII_TX_ER signals are synchronized to MII_TX_CLK.
MII_MDC Out Indicates MII management data clock
MII_MDO_ED Out Indicates MII management data output enable
MII_MDO Out Indicates MII management data out
MII_MDI In Indicates MII management data input
Table 10-2. GMII Ports
Port Name Port Group Direction Description
GMII_TXD[7:0] MAC_GMII_FABRIC Out GMII transmit data
GMII_TX_EN MAC_GMII_FABRIC Out GMII transmit data enable
GMII_TX_ER MAC_GMII_FABRIC Out GMII transmit data error
GMII_RXD[7:0] MAC_GMII_FABRIC Out GMII receive data
GMII_RX_ER MAC_GMII_FABRIC In GMII receive data error
GMII_RX_DV MAC_GMII_FABRIC In Indicates MII receive data valid
GMII_CRS MAC_GMII_FABRIC In Asynchronous carrier sense signal. Indicates at least one physical device transmits on the medium.
GMII_COL MAC_GMII_FABRIC In Asynchronous collision signal. Indicates more than one physical device transmits simultaneously on the medium.
GMII_RX_CLK MAC_GMII_FABRIC In Indicates GMII receive clock. 125 MHz for 1000-megabit mode, 25 MHz for 100-megabit mode, and 2.5 MHz for 10-megabit mode.
GMII_TX_CLK MAC_GMII_FABRIC In Indicates GMII transmit clock. 25 MHz for 100-megabit mode and 2.5-megabit for 10-megabit mode. GMIII_TXD, GMII_TX_EN, and GMII_TX_ER signals are synchronized to GMII_TX_CLK.
GMII_GTX_CLK MAC_GMII_FABRIC In Indicates gigabit 125 MHz transmit clock input for 1000-megabit mode. GMII_TXD, GMII_TX_EN, and GMII_TX_ER signals are synchronized to GMII_GTX_CLK.
GMII_MDC Out GMII management data clock
GMII_MDO_EN Out GMII management data output enable
GMII_MDO Out GMII management data out
GMII_MDI In GMII management data input
Table 10-3. TBI Ports
Port Name Port Group Direction Description
TBI_RCGF[9:0] MAC_TBI_FABRIC In MAC_RGGF is the 10-bit parallel receive data. The receive data byte 0 containing the comma character is byte aligned to 53,125 MHz receive byte clock used to latch the bytes 0 and 2 of the receive data word.
TBI_TCGF[9:0] MAC_TBI_FABRIC Out MAC_TCGF is the 10-bit parallel transmit data presented in the physical layer for serialization and transmission. The order of transmission is MAC_TCGF[0] first, followed by MAC_TCGF[1] through MAC_TCGF[9].
TBI_RX_CLKP0 MAC_TBI_FABRIC In TBI_RX_CLKP0 and TBI_RX_CLK1 are fed in from the fabric as two 62.5 MHz clocks, which are 180° out of phase with one another.
TBI_RX_CLKP1 MAC_TBI_FABRIC In Indicates 125 MHz clocks, which are 180° out of phase with one another.
TBI_GTX_CLK MAC_TBI_FABRIC In Indicates 125 MHz transmit clock from the fabric for 1000 Mbps mode.
TBI_MDI — In Indicates TBI management data clock
TBI_MDO — Out Indicates TBI management data output enable
TBI_MDO_EN — Out Indicates TBI management data out
TBI_MDC — Out Indicates TBI management data input
Important: Port names have the name of the MAC instance as a prefix, for example: MAC_GMII_TXD.

The following figure depicts the RMII, RGMII, RTBI, RevMII, and SMII derived from the available protocols by the appropriate wrapper in the fabric.

Figure 10-3. RMII, RGMII, RTBI, RevMII, SMII Derived from Available Protocols by Appropriate Wrapper in Fabric

The following figure depicts TBI to SerDes (EPCS Mode) for SGMII Interface.

Figure 10-4. TBI Brought to Fabric for EPCS Soft IP for SGMII Interface