10.3 TSEMAC PHY Interfaces

This section describes the MII, GMII, and TBI fabric PHY interfaces. The PHY interfaces are routed to the fabric onto MSIOs in case of MII, GMII, and SerDes I/Os in case of TBI. To implement the other PHY protocols within the fabric such as RMII, RGMII, RTBI, RevMII, and SMII, these PHY protocols may be derived from appropriate wrappers implemented in fabric, which converts PHY interface signals input to the FPGA fabric as shown in Figure 10-1. The EMAC can be configured through Libero® SoC MSS configurator by selecting the interface, line speed, and enabling the management interface PHY interface. On reset, MSS Ethernet MAC turns the auto-negotiate of the Ethernet PHY to OFF. Due to difference in protocol between MSS Ethernet MAC and Ethernet PHY, user has to handle the Ethernet PHY auto-negotiation through PHY driver code. The SGMII can be implemented by means of configuring the EMAC for the TBI operation. Figure 10-2 shows TBI pins are routed to SerDes, which is configured for EPCS mode to provide SGMII functionality.

The following tables list the port names, port groups, and direction information for the default supported MII, GMII, and TBI PHY interfaces. 

Table 10-1. MII Ports
Port NamePort GroupDirectionDescription
MII_TXD[3:0]MAC_MII_FABRICOutIndicates MII transmit data
MII_TX_ENMAC_MII_FABRICOutIndicates MII transmit data enable
MII_TX_ERMAC_MII_FABRICOutIndicates MII transmit data error
MII_RXD[3:0]MAC_MII_FABRICInIndicates MII receive data
MII_RX_ERMAC_MII_FABRICInIndicates MII receive data error
MII_RX_DVMAC_MII_FABRICInIndicates MII receive data valid
MII_CRSMAC_MII_FABRICInAsynchronous carrier sense signal. Indicates at least one physical device transmits on the medium.
MII_COLMAC_MII_FABRICInAsynchronous collision sense signal. Indicates more than one physical device transmits simultaneously on the medium.
MII_RX_CLKMAC_MII_FABRICInIndicates MII receive clock. 25 MHz for 100 Mbps mode and 
2.5 MHz for 10 Mbps mode.
MII_RX_CLKMAC_MII_FABRICInIndicates MII management transmit clock. 25 MHz for 100-Mbps mode and 2.5 MHz for 10 Mbps mode. MIII_TXD, MII_TX_EN, MII_TX_ER signals are synchronized to MII_TX_CLK.
MII_MDCOutIndicates MII management data clock
MII_MDO_EDOutIndicates MII management data output enable
MII_MDOOutIndicates MII management data out
MII_MDIInIndicates MII management data input
Table 10-2. GMII Ports
Port NamePort GroupDirectionDescription
GMII_TXD[7:0]MAC_GMII_FABRICOutGMII transmit data
GMII_TX_ENMAC_GMII_FABRICOutGMII transmit data enable
GMII_TX_ERMAC_GMII_FABRICOutGMII transmit data error
GMII_RXD[7:0]MAC_GMII_FABRICOutGMII receive data
GMII_RX_ERMAC_GMII_FABRICInGMII receive data error
GMII_RX_DVMAC_GMII_FABRICInIndicates MII receive data valid
GMII_CRSMAC_GMII_FABRICInAsynchronous carrier sense signal. Indicates at least one physical device transmits on the medium.
GMII_COLMAC_GMII_FABRICInAsynchronous collision signal. Indicates more than one physical device transmits simultaneously on the medium.
GMII_RX_CLKMAC_GMII_FABRICInIndicates GMII receive clock. 125 MHz for 1000-megabit mode, 25 MHz for 100-megabit mode, and 2.5 MHz for 10-megabit mode.
GMII_TX_CLKMAC_GMII_FABRICInIndicates GMII transmit clock. 25 MHz for 100-megabit mode and 2.5-megabit for 10-megabit mode. GMIII_TXD, GMII_TX_EN, and GMII_TX_ER signals are synchronized to GMII_TX_CLK.
GMII_GTX_CLKMAC_GMII_FABRICInIndicates gigabit 125 MHz transmit clock input for 1000-megabit mode. GMII_TXD, GMII_TX_EN, and GMII_TX_ER signals are synchronized to GMII_GTX_CLK.
GMII_MDCOutGMII management data clock
GMII_MDO_ENOutGMII management data output enable
GMII_MDOOutGMII management data out
GMII_MDIInGMII management data input
Table 10-3. TBI Ports
Port NamePort GroupDirectionDescription
TBI_RCGF[9:0]MAC_TBI_FABRICInMAC_RGGF is the 10-bit parallel receive data. The receive data byte 0 containing the comma character is byte aligned to 53,125 MHz receive byte clock used to latch the bytes 0 and 2 of the receive data word.
TBI_TCGF[9:0]MAC_TBI_FABRICOutMAC_TCGF is the 10-bit parallel transmit data presented in the physical layer for serialization and transmission. The order of transmission is MAC_TCGF[0] first, followed by MAC_TCGF[1] through MAC_TCGF[9].
TBI_RX_CLKP0MAC_TBI_FABRICInTBI_RX_CLKP0 and TBI_RX_CLK1 are fed in from the fabric as two 62.5 MHz clocks, which are 180° out of phase with one another.
TBI_RX_CLKP1MAC_TBI_FABRICInIndicates 125 MHz clocks, which are 180° out of phase with one another.
TBI_GTX_CLKMAC_TBI_FABRICInIndicates 125 MHz transmit clock from the fabric for 1000 Mbps mode.
TBI_MDI—InIndicates TBI management data clock
TBI_MDO—OutIndicates TBI management data output enable
TBI_MDO_EN—OutIndicates TBI management data out
TBI_MDC—OutIndicates TBI management data input
Important: Port names have the name of the MAC instance as a prefix, for example: MAC_GMII_TXD.

The following figure depicts the RMII, RGMII, RTBI, RevMII, and SMII derived from the available protocols by the appropriate wrapper in the fabric.

Figure 10-3. RMII, RGMII, RTBI, RevMII, SMII Derived from Available Protocols by Appropriate Wrapper in Fabric

The following figure depicts TBI to SerDes (EPCS Mode) for SGMII Interface.

Figure 10-4. TBI Brought to Fabric for EPCS Soft IP for SGMII Interface