10.4 EMAC Operation
Before any DMA transfers can be carried out, two sets of descriptors are needed to be initialized in the host memory. One descriptor is for the transmit operations and the other is for the receive operations. Each set of descriptors takes the form of a linked list typically closed to form a ring buffer.
For ease of handling by software, the transfers are handled using linked lists of transmit and receive descriptors. Transmit and receive descriptors define the buffer in the host memory for Tx operations and another for Rx operations.
The transfer of data in either direction typically uses a ring buffer defined within host memory. The ring buffer for the transmit operations is defined by a closed linked list of the Tx descriptors. The ring buffer for the receive operations is defined by a closed link list of the Rx descriptors. The descriptors act as pointers to the ring buffers. There are separate list of descriptors for both the transmit and receive processes. Each descriptor is in the host memory.
The two ring buffers are formed of an equal-sized segment, each of which is 32-bit aligned and is capable of storing a packet of up to the maximum size of packet transferred. Due to a limitation in the AHB-DMA controller, Ethernet jumbo frames are not supported.
The software can either use the DMA Interrupts generated or poll semaphore bits within the descriptors to maintain synchronization with the packet streams. The entry point into the buffer, used at the start of any sequence of transfers, is given by the descriptor picked out by the DMATx/RxDescriptor register.
The following table shows that each descriptor comprises of a sequence of three 32-bit memory locations.
| Address | Register | Function | Size |
|---|---|---|---|
| 0x0 | Table 10-5 | Start address for the packet data | 32 bits |
| 0x4 | Table 10-6 | Size of packet, Overrides and Empty Flag | 32 bits |
| 0x8 | Table 10-7 | Location of next descriptor | 32 bits |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:2] | PacketStartAddr[31:2] | 0x0 | Start address of the packet. |
| [1:0] | PacketStartAddr[1:0] | 0x0 | All transfers are 32-bit aligned in host memory. |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| 31 | Empty Flag | 0x0 | For the transmit operations, this bit indicates the availability of the data associated with the packet. For the receive operations, this bit indicates the availability of the specified location to store the received packet. The setting of this flag is used to validate the descriptor. |
| [30:21] | Reserved | 0x0 | Reserved |
| [20:16] | FTPP Overrides | 0x0 | The 5-bit field containing the FIFO transmit per-packet override flags signaled to the A-MCXFIFO during the packet transmission. The bits are encoded as follows: 20: FIFO transmit control frame flag. 19:18: FIFO transmit per-packet pad mode flag. 0x0: Do not pad transmit frame. 0x1: Pad all frames to 64 bytes and append FCS to all frames. 0x2: Reserved. 0x3: Reserved. 17: FIFO transmit per-packet generate FCS flag. 16: FIFO transmit per-packet enable flag. |
| [15:12] | Reserved | 0x0 | Reserved |
| [11:0] | PacketSize | 0x0 | For the transmit operations, the 12-bit field gives the size of packet to be transferred in bytes. In the receive operations, the DMA controller writes the number of bytes received to this field. The value of this field prior to the transfer being made is ignored. |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:2] | Next Descriptor[31:2] | 0x0 | The built-in DMA controller reads this register to discover the location in the host memory of the descriptor for the next packet in the sequence. The descriptors should form a closed linked list. |
| [1:0] | Next Descriptor[1:0] | 0x0 | All descriptors are 32-bit aligned in the host memory. |