10.7 EMAC Configuration Register Summary

Table 10-4 shows that each descriptor comprises a sequence of three 32-bit memory locations.

The following table summarizes each of the registers covered in this document. The EMAC base address is 0x40041000.

Table 10-13. EMAC M-AHB Register Map
Register Name	Address Offset	Register Type	Reset Value	Description
Table 10-20	0x180	R/W	0x0	Transmit control register
Table 10-21	0x184	R/W	0x0	Pointer to transmit descriptor
Table 10-22	0x188	R/W	0x0	Transmit status register
Table 10-23	0x18C	R/W	0x0	Receive control register
Table 10-24	0x190	R/W	0x0	Pointer to receive descriptor
Table 10-25	0x194	R/W	0x0	Receive status register
Table 10-26	0x198	R/W	0x0	Interrupt mask register
Table 10-27	0x19C	RO	0x0	Interrupts register

Table 10-14. EMAC PE-MCXMAC Register Map
Register Name	Address Offset	Register Type	Reset Value	Description
Table 10-28	0x00	R/W	0x80000000	MAC configuration register
Table 10-29	0x04	R/W	0x00007000	MAC configuration register
Table 10-30	0x08	R/W	0x40605060	Inter packet gap and interframe gap register
Table 10-31	0x0C	R/W	0x00A1F037	Definition of half-duplex register
Table 10-32	0x10	R/W	0x00000600	Sets the maximum frame size in both transmit and receive directions.
Reserved	0x14	R/W	0x0	Reserved
Reserved	0x18	R/W	0x0	Reserved
Table 10-33	0x1C	R/W	0x0	This test bit is used to predict back off times in Half-duplex mode. This allows the MAC to be paused for testing purpose only.
Table 10-34	0x20	R/W	0x0	This resets MII MGMT, determines MGMT clock frequency, and causes the MII MGMT to suppress preamble generation.
Table 10-35	0x24	R/W	0x0	MONITORS link fails
Table 10-36	0x28	R/W	0x0	This represents 5-bit PHY address field and 5-bit register address field.
Table 10-37	0x2C	WO	0x0	Control register for MII management write cycle that uses 16-bit data and the pre-configured PHY and register addresses.
Table 10-38	0x30	RO	0x0	Following an MII Mgmt read cycle, the 16-bit data can be read from this location.
Table 10-39	0x34	RO	0x0	This indicates MII management block is currently performing an MII Mgmt read or write cycle.
Table 10-40	0x38	R/W	0x0	This configures PERMII for 10 Mbps or 100 Mbps speed.
Table 10-41	0x3C	RO	0x0	This indicates the serial MII PHY has detected a jabber condition on the link. This also indicates the serial MII PHY has detected a valid link. This indicates the serial MII PHY is operating in full-duplex mode.
Table 10-42	0x40	R/W	0x0	The register fields hold the station address. Station address is the 48-bit programmed receive frame’s destination address.
Table 10-43	0x44	R/W	0x0	The register fields hold the station address. The station address is the 48-bit programmed receive frame’s destination address.

Table 10-15. EMAC A-MCXFIFO Register Map
Register Name	Address Offset	Register Type	Reset Value	Description
Table 10-44	0x48	R/W	0x0	Definition of A-MCXFIFO configuration register 0
Table 10-45	0x4C	R/W	0x0FFFFFFF	Definition of A-MCXFIFO configuration register 1
Table 10-46	0x50	R/W	0x1FFF1FFF	Definition of A-MCXFIFO configuration register 2
Table 10-47	0x54	R/W	0xFFF0FFF	Definition of A-MCXFIFO configuration register 3
Table 10-48	0x58	R/W	0x0	Definition of A-MCXFIFO configuration register 4
Table 10-49	0x5C	R/W	0x3FFFF	Definition of A-MCXFIFO configuration register 5
Table 10-50	0x60	R/W	0x0	The FIFO RAM access register 0 is intended for non-real-time RAM testing and debug
Table 10-51	0x64	R/W	0x0	The FIFO RAM access register 1 is intended for non-real-time RAM testing and debug
Table 10-52	0x68	R/W	0x0	The FIFO RAM access register 2 is intended for non-real-time RAM testing and debug
Table 10-53	0x6C	RO	0x0	The FIFO RAM access register 3 is intended for non-real-time RAM testing and debug
Table 10-54	0x70	R/W	0x0	The FIFO RAM access register 4 is intended for non-real-time RAM testing and debug
Table 10-55	0x74	R/W	0x0	The FIFO RAM access register 5 is intended for non-real-time RAM testing and debug
Table 10-56	0x78	R/W	0x0	The FIFO RAM access register 6 is intended for non-real-time RAM testing and debug
Table 10-57	0x7C	RO	0x0	The FIFO RAM access register 7 is intended for non-real-time RAM testing and debug

Table 10-16. EMAC PE-MSTAT Transmit and Receive Counters Register Map
Register Name	Address Offset	Register Type	Reset Value	Description
Table 10-58	0x80	R/W	0x0	Transmit and receive 64 byte frame counter
Table 10-59	0x84	R/W	0x0	Transmit and receive 65 to127 byte frame counter
Table 10-60	0x88	R/W	0x0	Transmit and receive 128 to 255 byte frame counter
Table 10-61	0x8C	R/W	0x0	Transmit and receive 256 to 511 byte frame counter
Table 10-62	0x90	R/W	0x0	Transmit and receive 512 to 1023 byte frame counter
Table 10-63	0x94	R/W	0x0	Transmit and receive 1024 to 1518 byte frame counter
Table 10-64	0x98	R/W	0x0	Transmit and receive 1519 to 1522 byte good VLAN frame count

Table 10-17. EMAC PE-MSTAT Receive Counters Register Map
Register Name	Address Offset	Register Type	Reset Value	Description
Table 10-65	0x9C	R/W	0x0	The statistic counter register is incremented by the byte count of all frames received.
Table 10-66	0XA0	R/W	0x0	Incremented for each frame received packet.
Table 10-67	0XA4	R/W	0x0	This is incremented for each frame received that has an integral 64 to 1518 length and contains a frame check sequence error.
Table 10-68	0XA8	R/W	0x0	This is incremented for each multicast good frame of lengths smaller than 1518 (non VLAN) or 1522 (VLAN) excluding broadcast frames.
Table 10-69	0xAC	R/W	0x0	This is incremented for each broadcast good frame of lengths smaller than 1518 (non VLAN) or 1522 (VLAN) excluding multicast frames.
Table 10-70	0XB0	R/W	0x0	This is incremented for each MAC control frame received.
Table 10-71	0XB4	R/W	0x0	This is incremented each time a valid PAUSE MAC control frame is received.
Table 10-72	0XB8	R/W	0x0	This is incremented each time a MAC control frame is received, which contains an op code other than a PAUSE.
Table 10-73	0xBC	R/W	0x0	This is incremented for each received frame from 64 to 1518, which contains an invalid FCS and is not an integral number of bytes.
Table 10-74	0XC0	R/W	0x0	This is incremented for each frame received in which the 802.3 length field does not match the number of data bytes actually received (46 – 1500 bytes).
Table 10-75	0XC4	R/W	0x0	This is incremented each time a valid carrier is present and at least one invalid data symbol is detected.
Table 10-76	0XC8	R/W	0x0	This is incremented each time a false carrier is detected.
Table 10-77	0xCC	R/W	0x0	This is incremented each time a frame is received, which is less than 64 bytes in length and contains a valid frame check sequence (FCS).
Table 10-78	0xD0	R/W	0x0	This is incremented each time a frame is received, which exceeds1518 (non VLAN) or 1522 (VLAN) bytes and contains a valid FCS.
Table 10-79	0xD4	R/W	0x0	This is incremented for each frame received, which is less than 64 bytes in length and contains an invalid FCS.
Table 10-80	0xD8	R/W	0x0	This is incremented for frames received, which exceed 1518 (non VLAN) or 1522 (VLAN) bytes and contains an invalid FCS.
Table 10-81	0xDC	R/W	0x0	This is incremented for frames received, which are streamed to system but are later dropped due to lack of system resources.

Table 10-18. EMAC PE-MSTAT Transmit Counters Register Map
Register Name	Address Offset	Register Type	Reset Value	Description
Table 10-82	0XE0	R/W	0x0	This is incremented for each transmitted byte including fragments of frames which are involved in collisions.
Table 10-83	0XE4	R/W	0x0	This is incremented for each transmitted packet.
Table 10-84	0XE8	R/W	0x0	This is incremented for each transmitted multicast valid frame.
Table 10-85	0xEC	R/W	0x0	This is incremented for each transmitted broadcast frame.
Table 10-86	0XF0	R/W	0x0	This is incremented each time a valid PAUSE MAC control frame is transmitted.
Table 10-87	0XF4	R/W	0x0	This incremented for each frame, which is deferred on its first transmission attempt.
Table 10-88	0XF8	R/W	0x0	This is incremented for aborted frames, which are deferred for an excessive period of time (3036 byte times).
Table 10-89	0xFC	R/W	0x0	This is incremented for each transmitted frame that experiences exactly one collision during the transmission.
Table 10-90	0x100	R/W	0x0	This is incremented for each transmitted frame that experiences 2 to 15 collisions (including any late collisions) during the transmission.
Table 10-91	0x104	R/W	0x0	This is incremented for each transmitted frame that experiences a late collision during a transmission attempt.
Table 10-92	0x108	R/W	0x0	This is incremented for each frame that experiences 16 collisions during the transmission and is aborted.
Table 10-93	0x10C	R/W	0x0	This is incremented by the number of collisions experienced during the transmission of a frame.
Table 10-94	0x110	R/W	0x0	This is incremented each time a valid PAUSE MAC control frame is transmitted and honored.
Table 10-95	0x114	R/W	0x0	This is incremented each time PAUSE frame is honored.
Table 10-96	0x118	R/W	0x0	This is incremented for each oversized transmitted frame with an incorrect FCS value.
Table 10-97	0x11C	R/W	0x0	This is incremented for each valid sized packet with an incorrect FCS value.
Table 10-98	0x120	R/W	0x0	This is incremented for each valid size frame with a Type Field signifying a Control frame.
Table 10-99	0x124	R/W	0x0	This is incremented for each oversized transmitted frame with a correct FCS value.
Table 10-100	0x128	R/W	0x0	This is incremented for each frame which is less than  64 bytes with a correct FCS value.
Table 10-101	0x12C	R/W	0x0	This is incremented for each frame which is less than  64 bytes, with an incorrect FCS value.
Table 10-102	0x130	RO	0x0	This indicates the transmit and receive counters and the receive counters carry the bits. The carry register bits are cleared on carry register write when the respective bit is asserted.
Table 10-103	0x134	RO	0x0	This indicates the transmit counters carry bits. The carry register bits are cleared on carry register write when the respective bit is asserted.
Table 10-104	0x138	R/W	0xFE01FFFF	The rollover condition of each transmit and receive counter and receive counters can be discreetly masked from causing an interrupt by internal masking.
Table 10-105	0x13C	R/W	0xFFFFF	The rollover condition of each transmit counter can be discreetly masked from causing an interrupt by internal masking.

Table 10-19. EMAC M-SGMII Register Map
Register Name	Address Offset	Register Type	Reset Value	Description
Table 10-106	0x00	R/W	0x0	This enables the loopback and the auto-negotiation. The PHY address for the M-SGMII is 0x1E.
Table 10-107	0x01	RO	0x0001	This enables the MF PREMABLE suppression enable. This indicates the auto-negotiation complete, associated PHY auto-negotiation ability, and link status. The PHY address for the M-SGMII is 0x1E.
RESERVED	0x02	R/W	0x0	Reserved
RESERVED	0x03	R/W	0x0	Reserved
Table 10-108	0x04	R/W	0x0	This indicates that the link is up when the M-SGMII is integrated into a PHY and is communicating with the SGMII module in a MAC. It also indicates the link is transferring data in full-duplex mode and link speed. The PHY address for the M-SGMII is 0x1E.
Table 10-109	0x05	RO	-	This indicates that the link is transferring data in  full-duplex mode. This also indicates the speed of the link. The PHY address for the M-SGMII is 0x1E.
Table 10-110	0x06	RO	0x0	This indicates that the device supports the next page function. This also indicates that the new page is received and stored in the applicable AN LINK PARTNER ABILITY or AN NEXT PAGE register. The PHY address for the M-SGMII is 0x1E.
Table 10-111	0x07	R/W	0x0	This indicates the additional next pages to follow and message page. Message pages are formatted pages, which carry a predefined message code that is enumerated in IEEE® 802.3u/Annex 28C. The PHY address for the M-SGMII is 0x1E.
Table 10-112	0x08	RO	-	The link partner asserts this bit to indicate additional Next Pages to follow. This indicates the message page and the link partner’s ability to comply with the message. The PHY address for the M-SGMII is 0x1E.
Table 10-113	0x0F	RO	0xA000	This indicates that the PHY can be operated in 1000BASE-X FULL-DUPLEX, 1000BASE-X HALF-DUPLEX, 1000BASE-T FULL-DUPLEX, 1000BASE-T HALF-DUPLEX. The PHY address for the M-SGMII is 0x1E.
Table 10-114	0x10	R/W	0x0	This enables the M-SGMII to transmit the jitter test patterns, which are defined in the IEEE 802.3z 36A. This selects the jitter pattern that is to be transmitted in diagnostics mode. The PHY address for the M-SGMII is 0x1E.
Table 10-115	0x11	R/W	0x0	This allows the auto-negotiation function to sense either a gigabit MAC in the auto-negotiation bypass mode or an older gigabit MAC without the auto-negotiation capability. This defines the M-SGMII as being in 1000BASE-X or SerDes mode. This allows the SerDes PHY to perform the code group alignment based upon the detection of a comma. The PHY address for the M-SGMII is 0x1E.

The following code snippet shows the minimal configuration required for MAC to make it functional in 1000 Mbps mode of operation.

CFG1= 32'h0000_0035 //Rx/Tx flow control enable, Rx/Tx-Enable
CFG2 = 32'h0000_7202 //Preamble=7, byteMode, CRC-enable
STATION_ADDRESS1 = 32'hA5A4_A3A2 //Station Address 1-4
STATION_ADDRESS2 = 32'hA1A0_0000 //Station Address 5-6
FIFO_CFG0 = 32'h0000_FF00 //Enable FIFO transmit and receive modules
FIFO_CFG3 = 32'h007F_FFFF // Tx-FIFO high watermark=128