10.1 Features

  • Supports tri-speeds: 10/100/1000 Mbps
  • Implements the carrier sense multiple access with the collision detection (CSMA/CD) algorithms defined by the Institute of Electrical and Electronics Engineers (IEEE®) 802.3 standard.
  • The advanced high-performance bus (AHB) master port for the direct memory access (DMA) transfers and AHB-slave port for the configuration space access.
  • The media independent interface (MII), gigabit media independent interface (GMII), and the ten-bit interface (TBI) for external PHY support.
  • MII/GMII/TBI loopback support.
  • 4 KB of TX buffer and 8 KB of RX buffer.
  • Both TX and RX Buffers are protected by single error correction and dual error detection (SECDED).
  • Standard Ethernet frames of 1522 bytes are supported. Jumbo frames of 9000 bytes are not supported.

The following figure shows the details of MSS. TSEMAC can function as an AHB master for DMA data transfers and as an AHB slave for configuring the TSEMAC from the master 
Arm® Cortex® -M3 processor or from the field programmable gate array (FPGA) fabric logic.

Figure 10-1. MSS Showing a TSEMAC