10.8 EMAC Register Bit Definitions

The following tables define the bit definitions of the registers present in EMAC.

Table 10-20. DMA_TX_CTRL
Bit Number	Name	Reset Value	Description
[31:1]	Reserved	0x0	Reserved
0	Transmit control	0x0	TxEnable: Set this bit to enable DMA transmit packet transfers. The bit is cleared by the built-in DMA controller whenever it encounters a Tx Underrun or Bus Error state.

Table 10-21. DMA_TX_DESC
Bit Number	Name	Reset Value	Description
[31:2]	Top 30 bits of Descriptor Address	0x0.	When TxEnable is set by the host, the built-in DMA controller reads this register to discover the location in the host memory of the first transmit packet descriptor.
[1:0]	Ignored by the DMA controller	0x0	All descriptors are 32-bit aligned in the host memory.

Table 10-22. DMA_TX_STATUS
Bit Number	Name	Reset Value	Description
[31:24]	Reserved	0x0	Reserved
[23:16]	TxPktCount	0x0	The 8-bit transmit packet counter that is incremented whenever the built-in DMA controller successfully transfers a packet, and is decremented whenever the host writes a '1' to bit '0' in this register.
[16:4]	Reserved	0x0	Reserved
3	BusError	0x0	When set, this indicates that a host slave split, retry or error response is received by the DMA controller.
2	Reserved	0x0	Reserved
1	TxUnderrun	0x0	Set whenever the DMA controller reads a '1' for the empty flag in the descriptor.
0	TxPktSent	0x0	When set, this indicates that one or more packets have been successfully transferred. Writing a '1' to this bit reduces the TxPktCount value by one. The bit is cleared whenever TxPktCount is zero.

Table 10-23. DMA_RX_CTRL
Bit Number	Name	Reset Value	Description
[31:1]	Reserved	0x0	Reserved
0	Rx Enable	0x0	Setting this bit enables DMA receive packet transfers. The bit is cleared by the built-in DMA controller whenever it encounters an Rx overflow or bus error state.

Table 10-24. DMA_RX_DESC
Bit Number	Name	Reset Value	Description
[31:1]	Top 30 bits of Descriptor Address	0x0	When RxEnable is set by the host, the built-in DMA controller reads this register to discover the location in the host memory of the first receive packet descriptor.
0	Ignored by the DMA controller	0x0	All descriptors are 32-bit aligned in the host memory.

Table 10-25. DMA_RX_STATUS
Bit Number	Name	Reset Value	Description
[31:24]	Reserved	0x0	Reserved
[23:16]	RxPktCount	0x0	The 8-bit receive packet counter that is incremented whenever the built-in DMA controller successfully transfers a packet, and is decremented whenever the host writes a “1” to bit zero of this register.
[16:4]	Reserved	0x0	Reserved
3	BusError	0x0	When set, this indicates that a host slave split, retry or error response is received by the DMA controller.
2	RxOverflow	0x0	Set whenever the DMA controller reads a zero empty flag in the descriptor it is processing.
1	Reserved	0x0	Reserved
0	RxPktReceived	0x0	When set, this indicates that one or more packets have been successfully transferred. Writing a “1” to this bit reduces the RxPktCount value by one. The bit is cleared whenever RxPktCount is zero.

Table 10-26. DMA_IRQ_MASK
Bit Number	Name	Reset Value	Description
[31:8]	Reserved	0x0	Reserved
7	Bus Error Mask	0x0	Setting this bit to “1” enables the Bus Error bit in the DMARxStatus register as an interrupt source.
6	Rx Overflow Mask	0x0	Setting this bit to “1” enables the RxOverflow bit in the DMARxStatus register as an interrupt source.
5	Reserved	0x0	Reserved
4	RxPktReceived Mask	0x0	Setting this bit to “1” enables the RxPktReceived bit in the DMARxStatus register as an interrupt source.
3	Bus Error Mask	0x0	Setting this bit to “1” enables the Bus Error bit in the DMATxStatus register as an interrupt source.
2	Reserved	0x0	Reserved
1	Tx Underrun Mask	0x0	Setting this bit to “1” enables the TxUnderrun bit in the DMATxStatus register as an interrupt source.
0	TxPktSent Mask	0x0	Setting this bit to “1” enables the TxPktSent bit in the DMATxStatus register as an interrupt source.

Table 10-27. DMA_IRQ
Bit Number	Name	Reset Value	Description
[31:8]	Reserved	0x0	Reserved
7	Bus Error	0x0	This is set to “1” to record a receive bus error interrupt when the Bus Error bit in the DMARxStatus register and bit 7 of the DMAIntrMask register are both set.
6	Rx Overflow	0x0	This is set to “1” to record an Rx overflow interrupt when the RxOverflow bit in the DMARxStatus register and bit 6 of the DMAIntrMask register are both set.
5	Reserved	0x0	Reserved
4	RxPktReceived	0x0	This is set to “1” to record a RxPktReceived interrupt when the RxPktReceived bit in the DMARxStatus register and bit 4 of the DMAIntrMask register are both set.
3	Bus Error	0x0	This is set to “1” to record a transmit bus error interrupt when the Bus Error bit in the DMATxStatus register and bit 3 of the DMAIntrMask register are both set.
2	Reserved	0x0	Reserved
1	Tx Underrun	0x0	This is set to “1” to record a Tx underrun interrupt when the TxUnderrun bit in the DMATxStatus register and bit 1 of the DMAIntrMask register are both set.
0	TxPktSent	0x0	This is set to “1” to record a TxPktSent interrupt when the TxPktSent bit in the DMATxStatus register and bit 0 of the DMAIntrMask register are both set.

Table 10-28. CFG1
Bit Number	Name	Reset Value	Description
31	SOFT RESET	0x1	Setting this bit will put all modules within the PE-MCXMAC in the reset except the Host Interface.
30	SIMULATION RESET	0x0	Setting this bit will reset those registers, such as the random backoff timer, which are not controlled by the normal resets (simulation only).
[29:20]	Reserved	0x0	Reserved
19	RESET RX MAC CONTROL	0x0	Setting this bit puts the PERMC Receive MAC control in reset.
18	RESET TX MAC CONTROL	0x0	Setting this bit puts the PETMC Transmit MAC control in reset.
17	RESET RX FUNCTION	0x0	Setting this bit puts the PERFN receive function block in reset. PERFN block performs the receive frame protocol.
16	RESET TX FUNCTION	0x0	Setting this bit puts the PETFN transmit function block in reset. PETFN block performs the frame transmission protocol.
[15:9]	Reserved	0x0	Reserved
8	LOOP BACK	0x0	Setting this bit causes the PETFN MAC transmit outputs to be looped back to the MAC receive inputs. Clearing this bit results in normal operation.
[7:6]	Reserved	0x0	Reserved
5	RECEIVE FLOW CONTROL ENABLE	0x0	Setting this bit causes the PERFN receive. MAC control to detect and act on PAUSE flow control frames. Clearing this bit causes the receive MAC control to ignore PAUSE flow control frames.
4	TRANSMIT FLOW CONTROL ENABLE	0x0	Setting this bit allows the PETMC transmit. MAC control sends PAUSE flow control frames when requested by the system. Clearing this bit prevents the transmit MAC control from sending flow control frames.
3	SYNCHRONIZED RECEIVE ENABLE	0x0	This field is read only and indicates that the receive enable is synchronized to the receive stream.
2	RECEIVE ENABLE	0x0	Setting this bit allows the MAC to receive frames from the PHY. Clearing this bit prevents the reception of the frames.
1	SYNCHRONIZED TRANSMIT ENABLE	0x0	This field is read only and indicates that the transmit enable is synchronized to the transmit stream.
0	TRANSMIT ENABLE	0x0	Setting this bit allows the MAC to transmit frames from the system. Clearing this bit prevents the transmission of the frames.

Table 10-29. CFG2
Bit Number	Name	Reset Value	Description
[31:16]	Reserved	0x0	Reserved
[15:12]	PREAMBLE LENGTH	0x7	This field determines the length of the preamble field of the packet in bytes. Default is ‘0x7’.
[9:8]	INTERFACE MODE	0x0	This field determines the type of interface the MAC is connected to. The Interface mode settings are as follows:
			Interface mode	Bit 9	Bit 8
			Reserved	0	0
			Nibble mode (10/100 Mbps MII/RMII/SMII, … )	0	1
			Byte mode (1000 Mbps GMII/TBI)	1	0
			Reserved	1	1
[7:6]	Reserved	0x0	Reserved
5	HUGE FRAME ENABLE	0x0	Set this bit to transmit and receive the frames that are longer than the MAXIMUM FRAME LENGTH. Clear this bit to have the MAC limits the length of frames at the MAXIMUM FRAME LENGTH value.
4	LENGTH FIELD CHECKING	0x0	Set this bit to cause the MAC to check the frame’s length field to ensure it matches the actual data field length. Clear this bit if no length field checking is desired.
3	Reserved	0x0	Reserved
2	PAD/CRC ENABLE	0x0	Set this bit to have the MAC pads all the short frames and appends a CRC to every frame whether or not padding is required. Clear this bit if frames, presented to the MAC, have a valid length and contain a CRC.
1	CRC ENABLE	0x0	Set this bit to have the MAC appends a CRC to all the frames. Clear this bit if frames that are presented to the MAC, have a valid length and contain a valid CRC. If the PAD/CRC ENABLE configuration bit or the per-packet PAD/CRC ENABLE is set, CRC ENABLE is ignored.
0	FULL-DUPLEX	0x0	Setting this bit configures the PE-MCXMAC to operate in  full-duplex mode. Clearing this bit configures the PE-MCXMAC to operate in half-duplex mode only.

Table 10-30. IFG
Bit Number	Name	Reset Value	Description
31	Reserved	0x0	Reserved
[30:24]	NON-BACK-TO-BACK INTER-PACKET-GAP PART 1 (IPGR1)	0x40	This programmable field represents the optional carrier Sense window, which is referenced in the IEEE 802.3/4.2.3.2.1 ‘Carrier Deference’. If a carrier is detected during the timing of IPGR1, the MAC defers to the carrier. However, the carrier becomes active after IPGR1; the MAC continues timing IPGR2 and transmit, knowingly causing a collision. This ensures fair access to the medium. The permitted range of values is 0x0 to IPGR2. Default is 0x40.
23	Reserved	0x0	Reserved
[22:16]	NON-BACK-TO-BACK INTER-PACKET-GAP PART 2 (IPGR2)	0x60	This programmable field represents the Non-Back-to-Back Inter-Packet-Gap in the bit times, which represent the minimum inter packet gap (IPG) of 96 bits.
[15:8]	MINIMUM IFG ENFORCEMENT	0x50	This programmable field represents the minimum size of management gap (IFG) to enforce between frames (expressed in bit times). A frame whose IFG is less than the programmed minimum IFG enforcement value is dropped. The default setting of 0x50 represents half of the nominal minimum IFG which is 160 bits.
7	Reserved	0x0	Reserved
[6:0]	BACK-TO-BACK INTER-PACKET-GAP	0x60	This programmable field represents the IPG between Back-to-Back packets (expressed in bit times). This is the IPG parameter used exclusively in full-duplex mode when two transmit packets are sent back-to-back. Set this field to the desired number of bits. The default setting of 0x60 represents the minimum IPG of 96 bits.

Table 10-31. HALF_DUPLEX
Bit Number	Name	Reset Value	Description
[31:24]	Reserved	0x0	Reserved
[23:20]	ALTERNATE BINARY EXPONENTIAL BACKOFF TRUNCATION	0xA	This field is used when ALTERNATE BINARY EXPONENTIAL BACKOFF ENABLE is set. The value programmed is substituted for the Ethernet standard value of ten. Default is ‘0xA’.
19	ALTERNATE BINARY EXPONENTIAL BACKOFF ENABLE	0x0	Setting this bit configures the Tx MAC to use the ALTERNATE BINARY EXPONENTIAL BACKOFF TRUNCATION setting instead of the 802.3 standard tenth collision. Clearing this bit causes the Tx MAC to follow the standard binary exponential backoff rule.
18	BACKPRESSURE NO BACKOFF	0x0	Setting this bit configures the Tx MAC to immediately re-transmit following a collision during back pressure operation. Clearing this bit causes the Tx MAC to follow the binary exponential backoff rule.
17	NO BACKOFF	0x0	Setting this bit configures the Tx MAC to immediately re-transmit following a collision. Clearing this bit causes the Tx MAC to follow the binary exponential backoff rule.
16	EXCESSIVE DEFER	0x1	Setting this bit configures the Tx MAC to allow the transmission of a packet that has been excessively deferred. Clearing this bit causes the Tx MAC to abort the transmission of a packet that has been excessively deferred.
[15:12]	RETRANSMISSION MAXIMUM	0xF	This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The standard specifies the maximum number of attempts to be 0xF (15d).
[11:10]	Reserved	0x0	Reserved
[9:0]	COLLISION WINDOW	0x37	This programmable field represents the slot time or collision window during which collisions might occur in a properly configured network. Since the collision window starts at the beginning of the transmission, the preamble and start frame delimiter (SFD) are included. The default of 0x37 (55d) corresponds to the count of the frame bytes at the end of the window.

Table 10-32. MAX_FRAME_LENGTH
Bit Number	Name	Reset Value	Description
[31:16]	Reserved	0x0	Reserved
[15:0]	MAXIMUM FRAME LENGTH	0x600	This programmable field sets the maximum frame size in both the transmit and receive directions.

Table 10-33. TEST
Bit Number	Name	Reset Value	Description
[31:4]	Reserved	0x0	Reserved
3	MAXIMUM FRAME LENGTH	0x0	Setting this bit causes the MAC to backoff for the maximum possible length of time. This test bit is used to predict the backoff times in half-duplex mode.
2	REGISTERED TRANSMIT FLOW ENABLE	0x0	Registered transmit half-duplex flow enable.
1	TEST PAUSE	0x0	Setting this bit allows the MAC to be paused via the host interface for the testing purposes.
0	SHORTCUT SLOT TIME	0x0	This bit allows the slot time counter to expire regardless of the current count. This bit is for the testing purposes only.

Table 10-34. MII_CONFIG
Bit Number	Name	Reset Value	Description
31	RESET MII MGMT	0x0	Setting this bit resets MII Mgmt. Clearing this bit allows MII Mgmt to perform Mgmt read/write cycles as requested via the Host Interface.
30:6	Reserved	0x0	Reserved
5	SCAN AUTO INCREMENT	0x0	Setting this bit causes MII Mgmt to continually read from a set of PHYs of contiguous address space. The starting address of the PHY is specified by the content of the PHY address field, which is recorded in the MII Mgmt Address register. Up to 31 PHY contiguous address space can be addressed. The last PHY, which is to be queried in this read sequence, is the one residing at address 0x31, after which the read sequence returns to the PHY, specified by the PHY address field.
4	PREAMBLE SUPPRESSION	0x0	Setting this bit causes MII Mgmt to suppress preamble generation and reduce the Mgmt cycle from 64 clocks to 32 clocks. This is in accordance with the IEEE 802.3/22.2.4.4.2. Clearing this bit causes MII Mgmt to perform Mgmt read/write cycles with the 64 clocks of preamble.
3	Reserved	0x0	Reserved
2:0	MGMT CLOCK SELECT	0x0	This field determines the clock frequency of the management data clock (MDC). Following are the MGMT Clock Select Encoding programming fields:
			Mgmt Clock Select	2	1	0
			Source Clock divided by 4	0	0	0
			Source Clock divided by 4	0	0	1
			Source Clock divided by 6	0	1	0
			Source Clock divided by 8	0	1	1
			Source Clock divided by 10	1	0	0
			Source Clock divided by 14	1	0	1
			Source Clock divided by 20	1	1	0
			Source Clock divided by 28	1	1	1

Table 10-35. MII_COMMAND
Bit Number	Name	Reset Value	Description
31:2	Reserved	0x0	Reserved
1	SCAN CYCLE	0x0	This bit causes MII Mgmt to perform Read cycles continuously. This is useful to monitor Link Fail.
0	READ CYCLE	0x0	This bit causes MII Mgmt to perform a single Read cycle. The Read data is returned in Register 0xC (MII Mgmt Read Data).

Table 10-36. MII_ADDRESS
Bit Number	Name	Reset Value	Description
[31:13]	Reserved	0x0	Reserved
[12:8]	PHY ADDRESS	0x00	This field represents the 5-bit PHY address field used in Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved).
[4:0]	REGISTER ADDRESS	0x00	This field represents the 5-bit register address field of Mgmt cycles. Up to 32 registers can be accessed.

Table 10-37. MII_CTRL
Bit Number	Name	Reset Value	Description
[31:16]	Reserved	0x0	Reserved
[15:0]	MII MGMT CONTROL	0x0	When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and register addresses from the MII Mgmt Register (0x0A).

Table 10-38. MII_STATUS
Bit Number	Name	Reset Value	Description
[31:16]	Reserved	0x0	Reserved
[15:0]	MII MGMT STATUS (PHY STATUS)	0x0	Following an MII Mgmt read cycle, the 16-bit data can be read from this location.

Table 10-39. MII_INDICATORS
Bit Number	Name	Reset Value	Description
[31:3]	Reserved	0x0	Reserved
2	NOT VALID	0x0	When “1” is returned, this indicates MII Mgmt Read cycle is not completed and the Read Data is not yet validated.
1	SCANNING	0x0	When “1” is returned, this indicates a scan operation (continuous MII Mgmt Read cycles) is in progress.
0	BUSY	0x0	When “1” is returned, this indicates MII Mgmt block is currently performing an MII Mgmt read or write cycle.

Table 10-40. INTERFACE_CTRL
Bit Number	Name	Reset Value	Description
31	RESET INTERFACE MODULE	0x0	Setting this bit resets the interface module. Clearing this bit allows for the normal operation. This bit can be used in the place of bits 23, 15, and 7, when just 1 interface module is connected.
[30:28]	Reserved	0x0	Reserved
27	TBIMODE	0x0	Setting this bit configures the A-RGMII module to expect TBI signals at the GMII interface. This bit should not be asserted unless this mode is being used.
26	GHDMODE	0x0	Setting this bit configures the A-RGMII module to expect half-duplex GMII at the GMII interface.
25	LHDMODE	0x0	Setting this bit configures the A-RGMII module to expect 10 or 100 half-duplex MII at the GMII interface. This bit should not be asserted unless this mode is being used.
24	PHY MODE	0x0	Setting this bit configures the PESMII serial MII module to be in PHY mode. Link characteristics are taken directly from the Rx segments supplied by the PHY. Clearing this bit configures the PESMII to be in MAC to MAC mode. In this configuration, the Serial MII module reverts to the pre-defined settings of 100 Mbps, full-duplex.
23	RESET PERMII	0x0	Setting this bit resets the PERMII module. Clearing this bit allows for normal operation.
[22:17]	Reserved	0x0	Reserved
16	SPEED	0x0	This bit configures the PERMII Reduced MII module with the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected.
15	RESET PE100X	0x0	This bit resets the 4B/5B symbol encipher/decipher logic.
[14:11]	Reserved	0x0	Reserved
10	FORCE QUIET	0x0	When enabled, the transmit data is cleared which allows the contents of the cipher to be the output. When cleared, the normal operation is enabled. This affects the 4B/5B symbol encipher/decipher logic module only.
9	NO CIPHER	0x0	When enabled, the raw transmit 5B symbols are transmitted without ciphering. When disabled, the normal ciphering occurs. This affects the 4B/5B symbol encipher/decipher logic module only.
8	DISABLE LINK FAIL	0x0	When enabled, the 330 ms Link Fail timer is disabled, allowing shorter simulations. Removes the 330 ms link-up time before reception of streams is allowed. When cleared, normal operation occurs. Affects 4B/5B symbol encipher/decipher logic module only.
7	Reserved	0x0	Reserved
[6:1]	Reserved	0x0	Reserved
0	ENABLE JABBER PROTECTION	0x0	This bit enables the jabber protection logic. Jabber is the condition where a transmitter is stuck on for longer than 50 ms to prevent other stations from transmitting.

Table 10-41. INTERFACE_STATUS
Bit Number	Name	Reset Value	Description
[31:11]	Reserved	0x0	Reserved
10	Reserved	0x0	Reserved
9	EXCESS DEFER	0x0	This bit sets when the MAC excessively defers a transmission. It clears when read. This bit latches high.
8	CLASH	0x0	When read as a “1”, the Serial MII module is in the MAC to MAC mode with the partner in 10 Mbps and/or half-duplex mode indicative of a configuration error. When read as a “0”, the Serial MII module is either in PHY mode or in a properly configured MAC to MAC mode.
7	JABBER	0x0	When read as a “1”, the Serial MII PHY detects a jabber condition on the link. When read as a “0”, the Serial MII PHY does not detect a jabber condition.
6	LINK OK	0x0	When read as a “1”, the Serial MII PHY detects a valid link. When read as a “0”, the Serial MII PHY does not detect a valid link.
5	FULL DUPLEX	0x0	When read as a “1”, the Serial MII PHY operates in full-duplex mode. When read as a “0”, the Serial MII PHY operates in half-duplex mode.
4	SPEED	0x0	When read as a “1”, the Serial MII PHY operates at 100 Mbps mode. When read as a “0”, the Serial MII PHY operates at 10 Mbps.
3	LINK FAIL	0x0	When read as a “1”, the MII Management module reads the PHY link fail register to be 1’. When read as a “0”, the MII Management module reads the PHY link fail register to be 0’. Note: For asynchronous host accesses, this bit must be read at least once every scan read cycle of the PHY.
2	Reserved	0x0	Reserved
1	Reserved	0x0	Reserved
0	Reserved	0x0	Reserved

Table 10-42. STATION_ADDRESS1
Bit Number	Name	Reset Value	Description
[31:24]	STATION ADDRESS	0x0	This field holds the first octet of the station address.
[23:16]	STATION ADDRESS	0x0	This field holds the second octet of the station address.
[15:8]	STATION ADDRESS	0x0	This field holds the third octet of the station address.
[7:0]	STATION ADDRESS	0x0	This field holds the fourth octet of the station address.

Table 10-43. STATION_ADDRESS2
Bit Number	Name	Reset Value	Description
[31:24]	STATION ADDRESS	0x0	This field holds the fifth octet of the station address.
[23:16]	STATION ADDRESS	0x0	This field holds the sixth octet of the station address.

Table 10-44. FIFO_CFG0
Bit Number	Name	Reset Value	Description
[31:21]	Reserved	0x0	Reserved
20	ftfenrply	0x0	This is a read only bit. When asserted, the FIFO transmit interface is enabled. When de-asserted, the FIFO transmit interface is disabled. The bit should be polled until it reaches the expected value.
19	stfenrply	0x0	This is a read only bit. When asserted, the FIFO PE-MCXMAC transmit interface module is enabled. When de-asserted, the FIFO PE-MCXMAC transmit interface module is disabled. The bit should be polled until it reaches the expected value.
18	frfenrply	0x0	This is a read only bit. When asserted, the FIFO receive interface module is enabled. When de-asserted, the FIFO receive interface module is disabled. The bit should be polled until it reaches the expected value.
17	srfenrply	0x0	This is a read only bit. When asserted, the FIFO PE-MCXMAC receive interface module is enabled. When de-asserted, the FIFO PE-MCXMAC receive interface module is disabled. The bit should be polled until it reaches the expected value.
16	wtmenrply	0x0	When asserted, the FIFO PE-MCXMAC watermark module is enabled. When de-asserted, the FIFO PE-MCXMAC watermark module is disabled. The bit should be polled until it reaches the expected value.
[15:13]	Reserved	0x0	Reserved
12	ftfenreq	0x0	When asserted, this bit requests to enable the FIFO fabric transmit interface module. When de-asserted, this bit requests to disable the FIFO Fabric transmit interface module.
11	stfenreq	0x0	When asserted, this bit requests to enable the FIFO  PE-MCXMAC transmit interface module. When de-asserted, this bit requests to disable the FIFO  PE-MCXMAC transmit interface module.
10	frfenreq	0x0	When asserted, this bit requests to enable the FIFO fabric receive interface module. When de-asserted, this bit requests to disable of the FIFO fabric receive interface module.
9	srfenreq	0x0	When asserted, this bit requests to enable the FIFO  PE-MCXMAC receive interface module. When de-asserted, this bit requests to disable the FIFO  PE-MCXMAC receive interface module.
8	wtmenreq	0x0	When asserted, this bit requests to enable the FIFO  PE-MCXMAC Watermark module. When de-asserted, this bit requests to disable the FIFO PE-MCXMAC watermark module.
[7:5]	Reserved	0x0	Reserved
4	hstrstft	0x0	When asserted, this bit places the FIFO Fabric transmit interface module in reset.
3	hstrstst	0x0	When asserted, this bit places the FIFO PE-MCXMAC transmit interface module in reset.
2	hstrstfr	0x0	When asserted, this bit places the FIFO Fabric receive interface module in reset.
1	hstrstsr	0x0	When asserted, this bit places the FIFO PE-MCXMAC receive interface module in reset.
0	hstrstwt	0x0	When asserted, this bit places the FIFO PE-MCXMAC watermark module in reset.

Table 10-45. FIFO_CFG1
Bit Number	Name	Reset Value	Description
[31:28]	Reserved	0x0	Reserved
[27:16]	cfgsrth[11:0]	0xFFF	This bit represents the minimum number of 4 byte locations, which are simultaneously stored in the receive RAM, relative to the beginning of the frame being input, before the fabric receive ready may be asserted.
[15:0]	cfgxoffrtx	0xFFFF	This bit represents the number of pause quanta after an XOFF pause frame is acknowledged, until the A-MCXFIFO re-asserts pause request if the A-MCXFIFO receive storage level remains higher than the low watermark.

Table 10-46. FIFO_CFG2
Bit Number	Name	Reset Value	Description
[31:29]	Reserved	0x0	Reserved
[28:16]	cfghwm	0x1FFF	This bit represents the maximum number of 4 byte words that are simultaneously stored in the receive RAM before the transmit flow control enables and pause value facilitates an XOFF pause control frame.
[15:13]	Reserved	0x0	Reserved
[12:0]	cfglwm	0x1FFF	This bit represents the minimum number of 4 byte words that are simultaneously stored in the receive RAM before transmit flow control enables and pause value facilitates an XON pause control frame in response to a previously transmitted XOFF pause control frame.

Table 10-47. FIFO_CFG3
Bit Number	Name	Reset Value	Description
[31:28]	Reserved	0x0	Reserved
[27:16]	cfghwmft	0xFFF	This hex value represents the maximum number of 4 byte locations, which are simultaneously stored in the transmit RAM before the fthwm is asserted. The fthwm is asserted whenever the amount of four byte locations, used in the transmit FIFO data RAM, exceeds the value programmed in the cfghwmft host register.
[15:12]	Reserved	0x0	Reserved
[11:0]	cfgftth	0xFFF	This bit represents the minimum number of 4 byte locations which are simultaneously stored in the transmit RAM, relative to the beginning of the frame being input, before transmit packet start of frame is asserted.

Table 10-48. FIFO_CFG4
Bit Number	Name	Reset Value	Description
[31:18]	Reserved	0x0	Reserved
[17:0]	hstfltrfrm	0x0	These configuration bits are used to signal the drop frame conditions internal to the A-MCXFIFO. The bits correspond to the receive statistics vector input to A-MCXFIFO on a one per one basis. Receive statistics vector indicates the characteristics of the current receive frame and is input to A-MCXFIFO. The setting of this bits along with their don’t care values in the hstfltrfrmdc not asserted, create the filter that drops the receive frame if the receive frame does not pass through the acceptable conditions. For example, if it is needed to drop a frame that contains a receive error, least significant fourth bit is set, and all receive frames that have frame receive error in receive statistics vector asserted are dropped. The hstfltrfrm bit and their corresponding receive statistics vector is as follows: Bit Description 17: System receive unicast address 16: Truncated frame 15: Receive long event 14: VLAN Tagged frame: frame’s length/type field contained 0x8100 which is the VLAN protocol identifier 13: Frame was an unsupported Op-code 12: Frame was a PAUSE control frame 11: Long event detected 10: Frame contained a dribble nibble 9: Broadcast address detected 8: Multicast address detected 7: Reception OK 6: Length/Type field was neither a length nor type 5: Frame’s length field out of range 4: Frame contained a CRC error 3: Frame contained a code error 2: False carrier previously seen 1: RX_DV event previously seen 0: Whether or not a prior packet was dropped

Table 10-49. FIFO_CFG5
Bit Number	Name	Reset Value	Description
[31:23]	Reserved	0x0	Reserved
22	cfghdplx	0x0	Assertion of this bit configures the A-MCXFIFO to enable the half-duplex as a flow control mechanism. De-assertion of this bit configures the A-MCXFIFO to enable pause frames as a flow control mechanism.
21	srfull	0x0	Assertion of this read-only bit indicates that the maximum capacity of the receive FIFO storage is met or exceeded.
20	hstsrfullclr	0x0	This bit should be written when it is desired to clear the srfull indicator bit. After the hstfullclr assertion, the srfull should be read until it becomes unasserted.
19	cfgbytmode	0x0	This bit should be asserted when the PE-MCXMAC is configured for GMII mode.
18	hstdrplt64	0x0	Setting this bit causes the frame to be dropped if a receive frame is less than 64 bytes in length.
[17:0]	hstfltrfrmdc	0X3FFFF	These configuration bits indicate which receive statistics vectors are don’t care for A-MCXFIFO frame drop circuitry. Receive statistics vector indicates the characteristics of the current receive frame. Setting of the hstfltrfrmdc bit, indicates a don’t care for the receive statistics vector bit. These bits corresponds to receive statistics vector on a one per one basis. The hstfltrfrmdc bit and their corresponding receive statistics vector is as follows: Bit Description 17: System receive unicast address 16: Truncated frame 15: Receive long event 14: VLAN Tagged frame: frame’s length/type field contained 0x8100 which is the VLAN protocol identifier 13: Frame was an unsupported Op-code 12: Frame was a PAUSE control frame 11: Long event detected 10: Frame contained a dribble nibble 9: Broadcast address detected 8: Multicast address detected 7: Reception OK 6: Length/Type field was neither a length nor type 5: Frame’s length field is out of range 4: Frame contained a CRC error 3: Frame contained a code error 2: False carrier previously seen 1: RX_DV event previously seen 0: Whether or not a prior packet was dropped

Table 10-50. FIFO_RAM_ACCESS0
Bit Number	Name	Reset Value	Description
31	hsttramwreq	0x0	Host transmit RAM write request
30	hsttramwack	0x0	Host transmit RAM write acknowledge
[29:24]	Reserved	0x0	Reserved
[23:16]	hsttramwdat [39:32]	0x0	Host transmit RAM write data This is the upper byte of the transmit FIFO RAM data that is written at the address of hsttramwadx[10:0], if hsttramwadx[12] is negated and hsttramwreq is asserted.
[15:13]	Reserved	0x0	Reserved
[12:0]	hsttramwadx	0x0	Host transmit RAM write address

Table 10-51. FIFO_RAM_ACCESS1
Bit Number	Name	Reset Value	Description
[31:0]	hsttramwdat	0x0	Host transmit RAM write data

Table 10-52. FIFO_RAM_ACCESS2
Bit Number	Name	Reset Value	Description
31	hsttramrreq	0x0	Host transmit RAM read request
30	hsttramrack	0x0	Host transmit RAM read acknowledge
[29:24]	Reserved	0x0	Reserved
[23:16]	hsttramrdat	0x0	Host transmit RAM read data. This is the upper byte of the transmit FIFO RAM data that was read at the address of the hsttramwadx[10:0], if the hsttramwadx[12] is negated and the hsttramwreq is asserted.
[15:13]	Reserved	0x0	Reserved
[12:0]	hsttramradx	0x0	Host transmit RAM read address

Table 10-53. FIFO_RAM_ACCESS3
Bit Number	Name	Reset Value	Description
[31:0]	hsttramrdat	0x0	Host transmit RAM read data

Table 10-54. FIFO_RAM_ACCESS4
Bit Number	Name	Reset Value	Description
31	hstrramwreq	0x0	Host receive RAM write request
30	hstrramwack	0x0	Host receive RAM write acknowledge
[29:24]	Reserved	0x0	Reserved
[23:16]	hstrramwdat[39:32]	0x0	Host receive RAM write data This is the upper byte of the receive FIFO RAM data that is written at the address of the hstrramwadx[11:0], if the hstrramwadx[13] is negated and the hstrramwreq is asserted.
[15:14]	Reserved	0x0	Reserved
[13:0]	hsttramwadx	0x0	Host receive RAM write address

Table 10-55. FIFO_RAM_ACCESS5
Bit Number	Name	Reset Value	Description
[31:0]	hstrramwdat	0x0	Host receive RAM write data

Table 10-56. FIFO_RAM_ACCESS6
Bit Number	Name	Reset Value	Description
31	hstrramrreq	0x0	Host receive RAM read request
30	hstrramrack	0x0	Host receive RAM read acknowledge
[29:24]	Reserved	0x0	Reserved
[23:16]	hstrramrdat [39:32]	0x0	Host receive RAM read data This is the upper byte of the receive FIFO RAM data that is read at the address of the hstrramwadx[10:0] if the hstrramwadx[13] is negated and the hstrramwreq is asserted.
[15:14]	Reserved	0x0	Reserved
[13:0]	hstrramradx [13:0]	0x0	Host receive RAM read address

Table 10-57. FIFO_RAM_ACCESS7
Bit Number	Name	Reset Value	Description
[31:0]	hstrramrdat	0x0	Host receive RAM read data

Table 10-58. TR64
Bit Number	Name	Reset Value	Description
[31:18]	Reserved	0x0	Reserved
[17:0]	TR64	0x0	Transmit and receive 64 byte frame counter: Incremented for each good or bad transmitted and received frame, which is 64 bytes in length inclusive (excluding framing bits but including FCS bytes).

Table 10-59. TR127
Bit Number	Name	Reset Value	Description
[31:18]	Reserved	0x0	Reserved
[17:0]	TR127	0x0	Transmit and receive 65 to 127 byte frame counter: Incremented for each good or bad, transmitted and received frame, which is 65 to 127 bytes in length inclusive (excluding framing bits but including FCS bytes).

Table 10-60. TR255
Bit Number	Name	Reset Value	Description
[31:18]	Reserved	0x0	Reserved
[17:0]	TR255	0x0	Transmit and receive 128 to 255 byte frame counter: Incremented for each good or bad, transmitted and received frame, which is 128 to 255 bytes in length inclusive (excluding framing bits but including FCS bytes).

Table 10-61. TR511
Bit Number	Name	Reset Value	Description
[31:18]	Reserved	0x0	Reserved
[17:0]	TR511	0x0	Transmit and receive 256 to 511 byte frame counter: Incremented for each good or bad, transmitted and received frame, which is 256 to 511 bytes in length inclusive (excluding framing bits but including FCS bytes).

Table 10-62. TR1K
Bit Number	Name	Reset Value	Description
[31:18]	Reserved	0x0	Reserved
[17:0]	TR1K	0x0	Transmit and receive 512 to 1023 byte frame counter: Incremented for each good or bad, transmitted and received frame, which is 512 to 1023 bytes in length inclusive (excluding framing bits but including FCS bytes).

Table 10-63. TRMAX
Bit Number	Name	Reset Value	Description
[31:18]	Reserved	0x0	Reserved
[17:0]	TRMAX	0x0	Transmit and receive 1024 to 1518 byte frame counter: Incremented for each good or bad, transmitted and received frame, which is 1024 to 1518 bytes in length inclusive (excluding framing bits but including FCS bytes).

Table 10-64. TRMGV
Bit Number	Name	Reset Value	Description
[31:18]	Reserved	0x0	Reserved
[17:0]	TRMGV	0x0	Transmit and receive 1519 to 1522 byte VLAN frame counter: Incremented for each good Virtual Local Area Network (VLAN) transmitted and received frame which is 1519 to 1522 bytes in length inclusive (excluding framing bits but including FCS bytes).

Table 10-65. RBYT
Bit Number	Name	Reset Value	Description
[31:24]	Reserved	0x0	Reserved
[23:0]	RBYT	0x0	Receive byte frame counter: The statistic counter register is incremented by the byte count of all the frames received, including those in the bad packets, excluding framing bits but including FCS bytes.

Table 10-66. RPKT
Bit Number	Name	Reset Value	Description
[31:18]	Reserved	0x0	Reserved
[17:0]	RPKT	0x0	Receive packet counter: Incremented for each frame received packet (including bad packets, all the unicast, broadcast, and multicast packets).

Table 10-67. RFCS
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	RFCS	0x0	Receive FCS error counter: Incremented for each frame received that has an integral 64 to 1518 length and contains a FCS error.

Table 10-68. RMCA
Bit Number	Name	Reset Value	Description
[31:18]	Reserved	0x0	Reserved
[17:0]	RMAC	0x0	Receive multicast packet counter: Incremented for each multicast good frame of lengths smaller than 1518 (non VLAN) or 1522 (VLAN) excluding the broadcast frames. This does not include range, length errors.

Table 10-69. RBCA
Bit Number	Name	Reset Value	Description
[31:22]	Reserved	0x0	Reserved
[21:0]	RBCA	0x0	Receive broadcast packet counter: Incremented for each broadcast good frame of lengths smaller than 1518 (non VLAN) or 1522 (VLAN) excluding the multicast frames. This does not look at range/length errors.

Table 10-70. RXCF
Bit Number	Name	Reset Value	Description
[31:18]	Reserved	0x0	Reserved
[17:0]	RXCF	0x0	Receive control frame packet counter: Incremented for each MAC control frame received (PAUSE and Unsupported).

Table 10-71. RXPF
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	RXPF	0x0	Receive PAUSE frame packet counter: Incremented each time a valid PAUSE MAC control frame is received.

Table 10-72. RXUO
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	RXUO	0x0	Receive unknown OP-code counter: Incremented each time a MAC control frame containing an op-code other than a PAUSE is received.

Table 10-73. RALN
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	RALN	0x0	Receive alignment error counter: Incremented for each received frame from 64 to 1518.This contains an invalid FCS and is not an integral number of bytes.

Table 10-74. RFLR
Bit Number	Name	Reset Value	Description
[31:16]	Reserved	0x0	Reserved
[15:0]	RFLR	0x0	Receive frame length error counter: Incremented for each frame received in which the 802.3 length field does not match with the number of the data bytes actually received (46-1500 bytes). The counter is not incremented if the length field is not a valid 802.3 length.

Table 10-75. RCDE
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	RCDE	0x0	Receive code error counter: Incremented each time a valid carrier is present and at least one invalid data symbol is detected.

Table 10-76. RCSE
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	RCSE	0x0	Receive false carrier counter: Incremented each time a false carrier is detected during idle, as defined by a 1 on RX_ER, and an ‘0xE’ on RXD. The event is reported along with the statistics generated on the next received frame. Only one false carrier condition can be detected and logged between frames.

Table 10-77. RUND
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	RUND	0x0	Receive undersize packet counter: Incremented each time a frame is received which is less than 64 bytes in length and contains a valid FCS. This does not include range, length errors.

Table 10-78. ROVR
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	ROVR	0x0	Receive oversize packet counter: Incremented each time a frame is received which exceeded 1518 (non VLAN) or 1522 (VLAN) and contains a valid FCS. This does not include range, length errors.

Table 10-79. RFRG
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	RFRG	0x0	Receive fragments counter: Incremented for each frame received which is less than 64 bytes in length and contains an invalid FCS. The received frame includes integral and non-integral lengths.

Table 10-80. RJBR
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	Reserved	0x0	Receive jabber counter: Incremented for frames received which exceed 1518 (non VLAN) or 1522 (VLAN) bytes and contains an invalid FCS. The received frame, includes alignment errors.

Table 10-81. RDRP
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	RDRP	0x0	Receive dropped packets counter: Incremented for frames received which are streamed to system but are later dropped due to lack of system resources.

Table 10-82. TBYT
Bit Number	Name	Reset Value	Description
[31:24]	Reserved	0x0	Reserved
[23:0]	TPKT	0x0	Transmit byte counter: Incremented by the number of bytes that are transmitted including fragments of frames, which are involved in collisions. This count does not include preamble/SFD or jam bytes.

Table 10-83. TPKT
Bit Number	Name	Reset Value	Description
[31:18]	Reserved	0x0	Reserved
[17:0]	TPKT	0x0	Transmit packet counter: Incremented for each transmitted packet (including bad packets, excessive deferred packets, excessive collision packets, late collision packets, all unicast, broadcast, and multicast packets).

Table 10-84. TMCA
Bit Number	Name	Reset Value	Description
[31:18]	Reserved	0x0	Reserved
[17:0]	TPKT	0x0	Transmit packet counter: Incremented for each transmitted packet (including bad packets, excessive deferred packets, excessive collision packets, late collision packets, all unicast, broadcast, and multicast packets).

Table 10-85. TBCA
Bit Number	Name	Reset Value	Description
[31:18]	Reserved	0x0	Reserved
[17:0]	TBCA	0x0	Transmit broadcast packet counter: Incremented for each broadcast frame transmitted (excluding multicast frames).

Table 10-86. TXPF
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	TXPF	0x0	Transmit PAUSE frame packet counter: Incremented each time a valid PAUSE MAC control frame is transmitted.

Table 10-87. TDFR
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	TDFR	0x0	Transmit deferral packet counter: Incremented for each frame, which is deferred on its first transmission attempt. This does not include frames involved in collisions.

Table 10-88. TEDF
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	TEDF	0x0	Transmit excessive deferral packet counter: Incremented for aborted frames which are deferred for an excessive period of time (3036 byte times).

Table 10-89. TSCL
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	TSCL	0x0	Transmit single collision packet counter: Incremented for each transmitted frame which experiences exactly one collision during the transmission.

Table 10-90. TMCL
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	TMCL	0x0	Transmit multiple collision packet counter: Incremented for each transmitted frame which experiences 2-15 collisions (including any late collisions).

Table 10-91. TLCL
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	TLCL	0x0	Transmit late collision packet counter: Incremented for each transmitted frame which experiences a late collision during a transmission attempt.

Table 10-92. TXCL
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	TXCL	0x0	Transmit excessive collision packet counter: Incremented for each frame that experiences 16 collisions during the transmission and is aborted.

Table 10-93. TNCL
Bit Number	Name	Reset Value	Description
[31:13]	Reserved	0x0	Reserved
[12:0]	TNCL	0X0	Transmit total collision counter: Incremented by the number of collisions experienced during the transmission of a frame due to simultaneous transmitting and receiving.

Table 10-94. TPFH
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	TPFH	0x0	Transmit PAUSE frames honored counter: Incremented each time a valid PAUSE MAC control frame is transmitted and honored.

Table 10-95. TDRP
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	TDRP	0x0	Transmit drop frame counter: Incremented each time the transmit PAUSE frame honored input to PE-MSTAT is asserted.

Table 10-96. TJBR
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	TJBR	0x0	Transmit jabber frame counter: Incremented for each oversized transmitted frame with an incorrect FCS value.

Table 10-97. TFCS
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	TFCS	0x0	Transmit FCS error counter: Incremented for each valid sized packet with an incorrect FCS value.

Table 10-98. TXCF
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	TXCS	0x0	Transmit control frame counter: Incremented for each valid size frame with a type field signifying a control frame.

Table 10-99. TOVR
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	TOVR	0x0	Transmit oversize frame counter: Incremented for each oversized transmitted frame with a correct FCS value.

Table 10-100. TUND
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	TUND	0x0	Transmit undersize frame counter: Incremented for each frame less than 64 bytes, with a correct FCS value.

Table 10-101. TFRG
Bit Number	Name	Reset Value	Description
[31:12]	Reserved	0x0	Reserved
[11:0]	TFRG	0x0	Transmit fragment counter: Incremented for each frame less than 64 bytes, with an incorrect FCS value.

Table 10-102. CAR1
Bit Number	Name	Reset Value	Description
31	C164	0x0	Carry register 1 TR64 counter carry bit
30	C1127	0x0	Carry register 1 TR127 counter carry bit
29	C1255	0x0	Carry register 1 TR255 counter carry bit
28	C1511	0x0	Carry register 1 TR511 counter carry bit
27	C11k	0x0	Carry register 1 TR1K counter carry bit
26	C1MAX	0x0	Carry register 1 TRMAX counter carry bit
25	C1MGV	0x0	Carry register 1 TRMGV counter carry bit
[24:17]	Reserved	0x0	Reserved
16	C1RBY	0x0	Carry register 1 RBYT counter carry bit
15	C1RPK	0x0	Carry register 1 RPKT counter carry bit
14	C1RFC	0x0	Carry register 1 RFCS counter carry bit
13	C1RMC	0x0	Carry register 1 RMCA counter carry bit
12	C1RBC	0x0	Carry register 1 RBCA counter carry bit
11	C1RXC	0x0	Carry register 1 RXCF counter carry bit
10	C1RXP	0x0	Carry register 1 RXPF counter carry bit
9	C1RXU	0x0	Carry register 1 RXUO counter carry bit
8	C1RAL	0x0	Carry register 1 RALN counter carry bit
7	C1RFL	0x0	Carry register 1 RFLR counter carry bit
6	C1RCD	0x0	Carry register 1 RCDE counter carry bit
5	C1RCS	0x0	Carry register 1 RCSE counter carry bit
4	C1RUN	0x0	Carry register 1 RUND counter carry bit
3	C1ROV	0x0	Carry register 1 ROVR counter carry bit
2	C1RFR	0x0	Carry register 1 RFRG counter carry bit
1	C1RJB	0x0	Carry register 1 RJBR counter carry bit
0	C1RDR	0x0	Carry register 1 RDRP counter carry bit

Table 10-103. CAR2
Bit Number	Name	Reset Value	Description
[31:20]	Reserved	0x0	Reserved
19	C2TJB	0x0	Carry register 2 TJBR counter carry bit
18	C2TFC	0x0	Carry register 2 TXFC counter carry bit
17	C2TCF	0x0	Carry register 2 TXCF counter carry bit
16	C2TOV	0x0	Carry register 2 TOVR counter carry bit
15	C2TUN	0x0	Carry register 2 TUND counter carry bit
14	C2TFG	0x0	Carry register 2 TFRG counter carry bit
13	C2TBY	0x0	Carry register 2 TBYT counter carry bit
12	C2TPK	0x0	Carry register 2 TPKT counter carry bit
11	C2TMC	0x0	Carry register 2 TMCA counter carry bit
10	C2TBC	0x0	Carry register 2 TBCA counter carry bit
9	C2TPF	0x0	Carry register 2 TXPF counter carry bit
8	C2TDF	0x0	Carry register 2 TDFR counter carry bit
7	C2TED	0x0	Carry register 2 TEDF counter carry bit
6	C2TSC	0x0	Carry register 2 TSCL counter carry bit
5	C2TMA	0x0	Carry register 2 TMCL counter carry bit
4	C2TLC	0x0	Carry register 2 TLCL counter carry bit
3	C2TXC	0x0	Carry register 2 TXCL counter carry bit
2	C2TNC	0x0	Carry register 2 TNCL counter carry bit
1	C2TPH	0x0	Carry register 2 TPFH counter carry bit
0	C2TDP	0x0	Carry register 2 TDRP counter carry bit

Table 10-104. CAM1
Bit Number	Name	Reset Value	Description
31	M164	0x1	Mask register 1 TR64 counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
30	M1127	0x1	Mask register 1 TR127 counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
29	M1255	0x1	Mask register 1 TR255 counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
28	M1511	0x1	Mask register 1 TR511 counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
27	M11k	0x1	Mask register 1 TR1K counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
26	M1MAX	0x1	Mask register 1 TRMAX counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
25	M1MGV	0x1	Mask register 1 TRMGV counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
[24:17]	Reserved	0x0	Reserved
16	M1RBY	0x1	Mask register 1 RBYT counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
15	M1RPK	0x1	Mask register 1 RPKT counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
14	M1RFC	0x1	Mask register 1 RFCS counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
13	M1RMC	0x1	Mask register 1 RMCA counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
12	M1RBC	0x1	Mask register 1 RBCA counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
11	M1RXC	0x1	Mask register 1 RXCF counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
10	M1RXP	0x1	Mask register 1 RXPF counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
9	M1RXU	0x1	Mask register 1 RXUO counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
8	M1RAL	0x1	Mask register 1 RALN counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
7	M1RFL	0x1	Mask register 1 RFLR counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
6	M1RCD	0x1	Mask register 1 RCDE counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
5	M1RCS	0x1	Mask register 1 RCSE counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
4	M1 RUN	0x1	Mask register 1 RUND counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
3	M1ROV	0x1	Mask register 1 ROVR counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
2	M1RFR	0x1	Mask register 1 RFRG counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
1	M1RJB	0x1	Mask register 1 RJBR counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
0	M1RDR	0x1	Mask register 1 RDRP counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit

Table 10-105. CAM2
Bit Number	Name	Reset Value	Description
[31:20]	Reserved	0x0	Reserved
19	M2TJB	0x1	Mask register 2 TJBR counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
18	M2TFC	0x1	Mask register 2 TXFC counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
17	M2TCF	0x1	Mask register 2 TXCF counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
16	M2TOV	0x1	Mask register 2 TOVR counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
15	M2TUN	0x1	Mask register 2 TUND counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
14	M2TFG	0x1	Mask register 2 TFRG counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
13	M2TBY	0x1	Mask register 2 TBYT counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
12	M2TPK	0x1	Mask register 2 TPKT counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
11	M2TMC	0x1	Mask register 2 TMCA counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
10	M2TBC	0x1	Mask register 2 TBCA counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
9	M2TPF	0x1	Mask register 2 TXPF counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
8	M2TDF	0x1	Mask register 2 TDFR counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
7	M2TED	0x1	Mask register 2 TEDF counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
6	M2TSC	0x1	Mask register 2 TSCL counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
5	M2TMA	0x1	Mask register 2 TMCL counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
4	M2TLC	0x1	Mask register 2 TLCL counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
3	M2TXC	0x1	Mask register 2 TXCL counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
2	M2TNC	0x1	Mask register 2 TNCL counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
1	M2TPH	0x1	Mask register 2 TPFH counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit
0	M2TDP	0x1	Mask register 2 TDRP counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit

Table 10-106. SGMII CONTROL
Bit Number	Name	Reset Value	Description
15	PHY RESET	0x0	Setting this bit causes the PETEX, PEREX, and PEANX sub-modules in the M-SGMII core to be reset. This bit is self-clearing.
14	LOOP BACK	0x0	Setting this bit causes the M-SGMII loopback. Clearing this bit results in normal operation.
13	Reserved	0x0	Reserved
12	AUTO-NEGOTIATION ENABLE	0x0	Setting this bit enables the auto-negotiation process.
[11:10]	Reserved	0x0	Reserved
9	RESET AUTO-NEGOTIATION	0x0	Setting this bit causes the auto-negotiation process to restart. This action is only available when auto-negotiation has been enabled.
[8:0]	Reserved	0x0	Reserved

Table 10-107. SGMII STATUS
Bit Number	Name	Reset Value	Description
[15:9]	Reserved	0x0	Reserved
8	EXTENDED STATUS	0x0	This bit returns “1” on read to indicate that the PHY status information is also contained in EXTENDED STATUS register.
7	Reserved	0x0	Reserved
6	MF PREMABLE SUPPRESSION ENABLE	0x0	This bit indicates whether the PHY is capable of handling MII management frames without the 32-bit preamble field. Returns “1” on read to indicate the support for suppressed preamble MII management frames.
5	AUTO-NEGOTIATION COMPLETE	0x0	This bit indicates that the auto-negotiation process is completed. Returns “0” on read when either the auto-negotiation process is underway or when the auto-negotiation function is disabled.
4	REMOTE FAULT	0x0	This bit returns “1” on read to indicate a remote fault condition has been detected between the M-SGMII and the PHY. This bit latches high in order for software to detect the condition. Each read of the STATUS register clears this bit.
3	AUTO-NEGOTIATION ABILITY	0x0	When “1”, this bit indicates that the M-SGMII has the ability to perform auto-negotiation. Returns “1” on read.
2	LINK STATUS		This bit indicates that a valid link is established between the  M-SGMII and the PHY. Returns “0” on read to indicate that there is no valid link is established. This bit latches low to allow software polling to detect a failure condition.
1	Reserved	0x0	Reserved
0	EXTENDED CAPABILITY	0x1	This bit returns “1” on read to indicates that the M-SGMII contains the extended set of registers (those beyond CONTROL and STATUS).

Table 10-108. AN SGMII ADVERTISEMENT
Bit Number	Name	Reset Value	Description
15	LINK UP	0x0	Assertion of this bit indicates that the link between M-SGMII and PHY is up.
[14:13]	Reserved	0x0	Reserved
12	FULL DUPLEX	0x0	Assertion of this bit indicates that the link between M-SGMII and PHY is up and transferring data in full-duplex mode.
[11:10]	LINK SPEED	0x0	Assertion of these two bits indicate that the link between M-SGMII and PHY is up. The following table shows the speed at which the link is transferring data:
			LINK SPEED [11]	LINK SPEED [10]	Capability
			1	1	Reserved
			1	0	1000 Mbps
			0	1	100 Mbps
			0	0	10 Mbps
[9:0]	Reserved	0x0	These bits must always be written ‘0000000001’ for correct M-SGMII operation.

Table 10-109. AN LINK PARTNER BASE PAGE ABILITY
Bit Number	Name	Reset Value	Description
15	LINK UP	0x0	When the M-SGMII is integrated to a MAC, such as the PE-MCXMAC, and is communicating with another SGMII PHY module, assertion of this bit indicates that the link is up. When the M-SGMII is integrated to a PHY and is not integrated to MAC, this bit is invalid.
[14:13]	Reserved	0x0	Reserved
12	FULL DUPLEX	0x0	Assertion of this bit indicates that LINK UP bit of the AN SGMII partner base page ability register is asserted and the link is transfers data in full-duplex mode.
[11:10]	LINK SPEED	0x0	Indicates the speed of the link as mentioned in the following table when LINK UP bit of the AN SGMII partner base page ability register is asserted.
			LINK SPEED [11]	LINK SPEED [10]	Capability
			1	1	Reserved
			1	0	1000 Mbps
			0	1	100 Mbps
			0	0	10 Mbps
[9:0]	Reserved	0x0	Reserved

Table 10-110. AN EXPANSION
Bit Number	Name	Reset Value	Description
[15:3]	Reserved	0x0	Reserved
2	NEXT PAGE ABLE	0x0	Returns “1” on read to indicate that the local device supports the next page function.
1	PAGE RECEIVED	0x0	Returns “1” on read to indicate that a new page has been received and stored in the applicable Table 10-109 or Table 10-111 register. This bit latches High for detection by software when polling. The bit is cleared on a read to the register.
0	Reserved	0x0	Reserved

Table 10-111. AN NEXT PAGE TRANSMIT
Bit Number	Name	Reset Value	Description
15	NEXT PAGE	0x0	Assert this bit to indicate additional Next Pages to follow. Clear the bit to indicate the last page.
14	Reserved	0x0	Reserved
13	MESSAGE PAGE	0x0	Assert this bit to indicate a Message Page. Clear the bit to indicate an Unformatted Page.
12	ACKNOWLEDGE 2	0x0	Used by the Next Page function to indicate that the device has the ability to comply with the message. Assert this bit if the local device will comply with the message. Clear the bit if the local device cannot comply with message.
11	TOGGLE	0x0	This bit is read only. Used to ensure synchronization with the Link Partner during Next Page exchange. This bit always takes the opposite value to the toggle bit of the previously exchanged Link Code Word. The initial value in the first Next Page transmitted is the inverse of bit 11 in the base Link Code Word.
[10:0]	MESSAGE / UNFORMATTED CODE FIELD	0x0	Message pages are formatted pages that carry a predefined Message Code, which is enumerated in IEEE 802.3u/Annex 28C. Unformatted code fields take an arbitrary value.

Table 10-112. AN NEXT PAGE TRANSMIT
Bit Number	Name	Description
15	NEXT PAGE	The link partner asserts this bit to indicate additional Next Pages to follow. When “0”, indicates last Next Page from link partner.
14	Reserved	Reserved
13	MESSAGE PAGE	When “1”, indicates Message Page. When “0”, indicates Unformatted Page.
12	ACKNOWLEDGE 2	Indicates link partner’s ability to comply with the message. When “1”, link partner complies with message. When “0”, link partner cannot comply with message.
11	TOGGLE	Used to ensure synchronization with the link partner during next page exchange. This bit always takes the opposite value to the toggle bit of the previously exchanged link code word. The initial value in the first next page transmitted is the inverse of bit 11 in the base link code word.
[10:0]	MESSAGE / UNFORMATTED CODE FIELD	Message pages are formatted pages that carry a predefined message code, which is enumerated in the IEEE 802.3u/Annex 28C. Unformatted code fields take an arbitrary value.

Table 10-113. EXTENDED STATUS
Bit Number	Name	Reset Value	Description
15	1000BASE-X FULL-DUPLEX	0x1	When “1”, indicates that the PHY can operate in 1000BASE-X  full-duplex mode. When “0”, indicates that the PHY cannot operate in 1000BASE-X full-duplex mode.
14	1000BASE-X HALF-DUPLEX	0x0	When “1”, indicates that the PHY can operate in 1000BASE-X  half-duplex mode. When “0”, indicates that the PHY cannot operate in 1000BASE-X half-duplex mode.
13	1000BASE-T FULL-DUPLEX	0x1	When “1”, indicates that the PHY can operate in 1000BASE-T  full-duplex mode. When “0”, indicates that the PHY cannot operate in 1000BASE-T full-duplex mode. Returns “1” on read.
12	1000BASE-T HALF-DUPLEX	0x0	When “1”, indicates that the PHY can operate in 1000BASE-T  half-duplex mode. When “0”, indicates PHY cannot operate in 1000BASE-T half-duplex mode.
[11:0]	Reserved	0x0	Reserved

Table 10-114. JITTER DIAGNOSTICS
Bit Number	Name	Reset Value	Description
15	JITTER DIAGNOSTIC ENABLE	0x0	Set this bit to enable the M-SGMII to transmit the jitter test patterns defined in IEEE 802.3z 36A. Clear this bit to enable normal transmit operation.
[14:12]	JITTER PATTERN SELECT	0x0	Selects the jitter pattern to be transmitted in Diagnostics mode. Encoding of this field is as follows:
			Jitter Pattern Select	Bit 14	Bit 13	Bit 12
			User defined custom pattern	0	0	0
			Annex 36A defined high frequency	0	0	1
			Annex 36A defined mixed frequency	0	1	0
			Custom defined low frequency	0	1	1
			Random jitter pattern	1	0	0
			Annex 36A defined low frequency	1	0	1
			Reserved	1	1	0
			Reserved	1	1	1
[11:10]	Reserved	0x0	Reserved
[9:0]	CUSTOM JITTER PATTERN	0x0	Used in conjunction with JITTER PATTERN SELECT and JITTER DIAGNOSTIC ENABLE. Set this field to the desired custom pattern, which is transmitted continuously.

Table 10-115. TBI CONTROL
Bit Number	Name	Reset Value	Description
15	SOFT RESET	0x0	This bit resets the functional modules in the M-SGMII. Clear it for normal operation. Its default is “0”.
14	SHORTCUT LINK TIMER	0x0	Set this bit to reduce the amount of simulation time needed to time the 1.6 ms Link Timer. Clear it for normal operation.
13	DISABLE RECEIVE RUNNING DISPARITY	0x0	Set this bit to disable the running disparity calculation and checking in the receive direction. This bit must be “0” for correct  M-SGMII operation.
12	DISABLE TRANSMIT RUNNING DISPARITY	0x0	Set this bit to disable the running disparity calculation and checking in the transmit direction. This bit must be “0” for correct M-SGMI operation.
[11:9]	Reserved	0x0	Reserved
8	AUTO-NEGOTIATION SENSE	0x0	Set this bit to allow the auto-negotiation for 1000BASE-X, which is used to exchange information between link partners. Clear this bit when IEEE 802.3z Clause 37 behavior is desired, which results in the link not coming up.
[7:6]	Reserved	0x0	Reserved
5	RECEIVE CLOCK SELECT	0x0	Set this bit to configure the M-SGMII to accept a 125 MHz receive clock from the SerDes PHY. Clear this bit to allow the M-SGMII to accept dual split-phase 62.5 MHz receive clocks. This bit must be “0” for correct M-SGMII operation.
4	GMII MODE	0x0	When cleared, this bit defines the M-SGMII as being in 1000BASE-X SerDes mode. This bit must be “0” for correct  M-SGMII operation.
[3:2]	Reserved	0x0	Reserved
1	ENABLE WRAP	0x0	Set this bit to configure the SerDes in Loopback mode. Clear this bit to permit normal operation.
0	ENABLE COMMA DETECT	0x0	Set this bit to allow the SerDes PHY to perform code group alignment based upon the detection of a comma.